ISL76161AVZ,ISL76161AVZ pdf中文资料,ISL76161AVZ引脚图,ISL76161AVZ电路-Datasheet-电子工程世界

供应商	器件名称	价格	最低购买	库存
	ISL76161AVZ	-	-	点击查看	点击购买

®

ISL76161

Data Sheet

September 9, 2008

FN6720.1

12-Bit, +3.3V, 130MSPS, High Speed D/A

Converter

The ISL76161 is a 12-bit, 130MSPS (Mega-Samples Per

Second), CMOS, high speed, low power, D/A (digital to

analog) converter, designed specifically for use in radar

systems or high performance communication systems, such

as base transceiver stations utilizing 2.5G or 3G cellular

protocols.

Features

• High Speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130MSPS

• Low Power . . . . . 103mW with 20mA Output at 130MSPS

• Adjustable Full Scale Output Current . . . . . 2mA to 20mA

• Excellent Spurious Free Dynamic Range

(73dBc to Nyquist, f

S

= 130MSPS, f

OUT

= 10MHz)

• Automotive Qualified Component

• Extended Temperature Operation: -40°C to +105°C

Pinout

ISL76161

(28 LD TSSOP)

TOP VIEW

D11 (MSB) 1

D10 2

D9 3

D8 4

D7 5

D6 6

D5 7

D4 8

D3 9

D2 10

D1 11

D0 (LSB) 12

DCOM 13

DCOM 14

28 CLK

27 DV

DD

26 DCOM

25 NC

24 AV

DD

23 COMP

22 IOUTA

21 IOUTB

20 ACOM

19 NC

18 FSADJ

17 REFIO

16 REFLO

15 SLEEP

• +3.3V Power Supply

• 3V LVCMOS Compatible Inputs

• UMTS Adjacent Channel Power = 70dB at 19.2MHz

• EDGE/GSM SFDR = 90dBc at 11MHz in 20MHz Window

• Pb-Free (RoHS Compliant)

Applications

• Automotive Radar Systems

- 24GHz and 77GHz Radar for Adaptive Cruise Control

• Cellular Infrastructure - Single or Multi-Carrier: IS-136,

IS-95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA

• Wireless Communication Systems

• High Resolution Imaging Systems

• Arbitrary Waveform Generators

Ordering Information

PART NUMBER

(Note 1)

ISL76161AVZ

ISL76161AVZ-T*

ISL76161AVZ-TK*

PART MARKING

ISL76161 AVZ

CLOCK SPEED

130MHz

TEMP. RANGE

(°C)

-40 to +105

PACKAGE

(Pb-Free, Note 2)

28 Ld TSSOP

28 Ld TSSOP Tape and Reel

PKG. DWG. #

M28.173

*Please refer to TB347 for details on reel specifications.

NOTES:

1. These parts have been qualified in accordance with AECQ100 rev F recommendations, some exceptions may apply. Request qualification plan

for further details.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC

J STD-020.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

|

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL76161

Typical Applications Circuit

ISL76161

(25, 19) NC

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D11 (MSB) (1)

D10 (2)

D9 (3)

D8 (4)

D7 (5)

D6 (6)

D5 (7)

D4 (8)

D3 (9)

D2 (10)

D1 (11)

D0 (LSB) (12)

CLK (28)

DCOM (26, 13, 14)

(20) ACOM

BEAD

+

10µF

10µH

0.1µF

DV

DD

(27)

(24) AV

DD

(23) COMP

0.1μF

FERRITE

BEAD

10µH

0.1µF

10µF

+

+3.3V (V

DD

)

1:1, Z1:Z2

(22) IOUTA

(21) IOUTB

50Ω

(18) FSADJ

R

SET

(50Ω)

REPRESENTS

ANY 50Ω LOAD

1.94kΩ

(15) SLEEP

(16) REFLO

(17) REFIO

0.1µF

ONE CONNECTION

DCOM

ACOM

50Ω

Functional Block Diagram

IOUTA

IOUTB

CASCODE

(LSB) D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

UPPER

5-BIT

DECODER

COMP

CLK

INT/EXT

VOLTAGE

REFERENCE

38

SWITCH

MATRIX

38

INPUT

LATCH

CURRENT

SOURCE

7 LSBs

+

31 MSB

SEGMENTS

D10

D11

BIAS

GENERATION

REFLO REFIO

FSADJ

SLEEP

2

FN6720.1

September 9, 2008

ISL76161

Pin Descriptions

PIN NO.

1 through 12

PIN NAME

D11 (MSB) through

D0 (LSB)

SLEEP

DESCRIPTION

Digital Data Bit 11, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).

15

Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep

pin has internal 20µA active pull-down current.

Connect to analog ground to enable internal 1.2V reference or connect to AV

DD

to disable internal

reference.

Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is

enabled. Use 0.1µF cap to ground when internal reference is enabled.

Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output

Current = 32 x V

FSADJ

/R

SET

.

No Connect. These should be grounded, but can be left disconnected.

The complementary current output of the device. Full scale output current is achieved when all input bits

are set to binary 0.

Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.

Connect 0.1µF capacitor to ACOM.

Analog Supply (+3.0V to +3.6V).

Connect to Analog Ground.

Connect to Digital Ground.

Digital Supply (+3.0V to +3.6V).

Clock Input.

16

REFLO

17

REFIO

18

FSADJ

19, 25

21

NC

IOUTB

22

23

24

20

13, 14, 26

27

28

IOUTA

COMP

AV

DD

ACOM

DCOM

DV

DD

CLK

3

FN6720.1

September 9, 2008

ISL76161

Absolute Maximum Ratings

Digital Supply Voltage DV

DD

to DCOM . . . . . . . . . . . . . . . . . +4.0V

Analog Supply Voltage AV

DD

to ACOM. . . . . . . . . . . . . . . . . . +4.0V

Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DV

DD

+ 0.3V

Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV

DD

+ 0.3V

Analog Output Current (I

OUT

) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA

Thermal Information

Thermal Resistance (Typical, Note 3)

θ

JA

(°C/W)

TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .

84

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTE:

3.

θ

JA

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications

AV

DD

= DV

DD

= +3.3V, V

REF

= Internal 1.2V, IOUTFS = 20mA, T

A

= +25°C for All Typical Values; Parameters

with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established

by characterization and are not production tested.

T

A

= -40°C TO +105°C

PARAMETER

SYSTEM PERFORMANCE

Resolution

Integral Linearity Error, INL

Differential Linearity Error, DNL

Offset Error, I

OS

Offset Drift Coefficient

Full Scale Gain Error, FSE

TEST CONDITIONS

MIN

TYP

MAX

UNITS

12

“Best Fit” Straight Line (Note 9)

(Note 9)

IOUTA (Note 9)

(Note 9)

With External Reference (Notes 4, 9)

With Internal Reference (Notes 4, 9)

-1.25

-1

-0.006

-

-3

-

±0.5

-

0.1

±0.5

±50

±100

20

2

1.25

-1.0

-

+1.25

+1

+0.006

-

+3

-

Bits

LSB

% FSR

ppm

FSR/°C

% FSR

ppm

FSR/°C

ppm

FSR/°C

mA

V

Full Scale Gain Drift

With External Reference (Note 9)

With Internal Reference (Note 9)

Full Scale Output Current, I

FS

R

SET

= 1.94kΩ (Maximum FS output)

R

SET

= 20kΩ (Minimum FS output)

Output Voltage Compliance - High

Voltage Limit

Output Voltage Compliance - Low

Voltage Limit

DYNAMIC CHARACTERISTICS

Maximum Clock Rate, f

CLK

Output Rise Time

Output Fall Time

Output Capacitance

Output Noise

IOUTFS = 20mA

IOUTFS = 2mA

Full Scale Step

130

-

150

1.5

10

50

30

-

MHz

ns

pF

pA/√Hz

4

FN6720.1

September 9, 2008

ISL76161

Electrical Specifications

AV

DD

= DV

DD

= +3.3V, V

REF

= Internal 1.2V, IOUTFS = 20mA, T

A

= +25°C for All Typical Values; Parameters

with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established

by characterization and are not production tested.

(Continued)

T

A

= -40°C TO +105°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

AC CHARACTERISTICS

(Using Figure 12 with R

DIFF

= 100Ω, R

LOAD

= R

A

= R

B

= 50Ω, Full Scale Output = -2.0dBm)

Spurious Free Dynamic Range,

SFDR Within a Window

Spurious Free Dynamic Range,

SFDR to Nyquist (f

CLK

/2)

f

CLK

= 130MSPS, f

OUT

= 20.2MHz, 20MHz Span (Notes 6, 8)

f

CLK

= 130MSPS, f

OUT

= 50.5MHz (Notes 6, 8)

f

CLK

= 130MSPS, f

OUT

= 40.4MHz (Notes 6, 8)

f

CLK

= 130MSPS, f

OUT

= 20.2MHz (Notes 6, 9)

f

CLK

= 130MSPS, f

OUT

= 10.1MHz (Notes 6, 8)

f

CLK

= 130MSPS, f

OUT

= 5.05MHz, T = +25°C (Notes 6, 8)

f

CLK

= 130MSPS, f

OUT

= 5.05MHz, T = -40°C to +105°C (Notes 6, 8)

f

CLK

= 100MSPS, f

OUT

= 40.4MHz (Notes 6, 8)

f

CLK

= 80MSPS, f

OUT

= 30.3MHz (Notes 6, 8)

f

CLK

= 80MSPS, f

OUT

= 20.2MHz (Notes 6, 8)

f

CLK

= 80MSPS, f

OUT

= 10.1MHz (Notes 6, 8, 10)

f

CLK

= 80MSPS, f

OUT

= 5.05MHz (Notes 6, 8)

f

CLK

= 50MSPS, f

OUT

= 20.2MHz (Notes 6, 8)

f

CLK

= 50MSPS, f

OUT

= 10.1MHz (Notes 6, 8)

f

CLK

= 50MSPS, f

OUT

= 5.05MHz (Notes 6, 8)

Spurious Free Dynamic Range,

SFDR in a Window with Eight Tones

f

CLK

= 130MSPS, f

OUT

= 17.5MHz to 27.9MHz, 1.3MHz Spacing,

35MHz Span (Notes 6, 8)

f

CLK

= 80MSPS, f

OUT

= 10.8MHz to 17.2MHz, 811kHz Spacing,

15MHz Span (Notes 6, 8)

f

CLK

= 50MSPS, f

OUT

= 6.7MHz to 10.8MHz, 490kHz Spacing,

10MHz Span (Notes 6, 8)

Spurious Free Dynamic Range,

f

CLK

= 78MSPS, f

OUT

= 11MHz, in a 20MHz Window, RBW = 30kHz

SFDR in a Window with EDGE or GSM (Notes 6, 8, 10)

Adjacent Channel Power Ratio,

ACPR with UMTS

VOLTAGE REFERENCE

Internal Reference Voltage, V

FSADJ

Internal Reference Voltage Drift

Internal Reference Output Current

Sink/Source Capability

Reference Input Impedance

Reference Input Multiplying Bandwidth (Note 8)

DIGITAL INPUTS

D11-D0, CLK

(Note 5)

0.7 *

DV

DD

-

-25

-20

-10

-

0.3 *

DV

DD

+25

+20

+10

V

µA

Reference is not intended to be externally loaded

Pin 18 Voltage with Internal Reference

1.2

-

1.23

±40

0

1

1.0

1.3

-

V

ppm/°C

µA

MΩ

MHz

f

CLK

= 76.8MSPS, f

OUT

= 19.2MHz, RBW = 30kHz (Notes 6, 8, 10)

-

70

67

-

85

57

62

69

73

77

-

60

63

69

70

76

68

73

77

68

75

77

90

70

-

dBc

dB

Input Logic High Voltage with

3.3V Supply, V

IH

Input Logic Low Voltage with

3.3V Supply, V

IL

Sleep Input Current, I

IH

Input Logic Current, I

IH, IL

Clock Input Current, I

IH, IL

5

FN6720.1

September 9, 2008

ISL76161AVZ

ISL76161AVZ在线购买

ISL76161AVZ概述

文档预览

ISL76161AVZ相似产品对比

推荐资源