General Description ................................................................................................................................................. 8
Pin and Marking Diagram ................................................................................................................................9
Absolute Maximum Ratings ........................................................................................................................... 11
2.4.1. Power Consumption .................................................................................................................................. 12
2.4.2. Frequency Synthesis................................................................................................................................. 12
2.4.4. Digital Specification ................................................................................................................................... 14
Power Supply Strategy .................................................................................................................................. 15
Frequency Synthesis ..................................................................................................................................... 15
3.3.4. Lock Time ..................................................................................................................................................17
3.4.2. LNA - Single to Differential Buffer .............................................................................................................18
3.4.3. Automatic Gain Control ............................................................................................................................. 18
3.4.7. DC Cancellation ........................................................................................................................................22
3.4.8. Complex Filter - OOK ................................................................................................................................ 22
3.4.13. OOK Demodulator ...................................................................................................................................25
3.4.14. Bit Synchronizer ......................................................................................................................................27
3.4.15. Frequency Error Indicator........................................................................................................................ 27
3.4.16. Automatic Frequency Correction............................................................................................................. 28
3.4.17. Optimized Setup for Low Modulation Index Systems.............................................................................. 29
3.4.18. Temperature Sensor ...............................................................................................................................30
4.3.3. End of Cycle Actions ................................................................................................................................. 35
Data Processing .................................................................................................................................................... 38
5.1.2. Data Operation Modes .............................................................................................................................. 38
5.2.
Control Block Description............................................................................................................................... 39
5.2.3. Sync Word Recognition............................................................................................................................. 41
Digital IO Pins Mapping .................................................................................................................................43
5.3.1. DIO Pins Mapping in Continuous Mode .................................................................................................... 43
5.3.2. DIO Pins Mapping in Packet Mode ........................................................................................................... 43
5.4.1. General Description................................................................................................................................... 44
5.5.1. General Description................................................................................................................................... 45
5.5.2. Packet Format ........................................................................................................................................... 45
5.5.7. DC-Free Data Mechanisms....................................................................................................................... 51
6.
Configuration and Status Registers ....................................................................................................................... 53
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
7.
7.1.
7.2.
General Description ....................................................................................................................................... 53
Common Configuration Registers ..................................................................................................................56
Temperature Sensor Registers...................................................................................................................... 66
Test Registers................................................................................................................................................ 66
Reset of the Chip ........................................................................................................................................... 67
Application Information .......................................................................................................................................... 67
Packaging Information ........................................................................................................................................... 70
OOK Floor Threshold Default Setting ............................................................................................................ 73
AFC Control ................................................................................................................................................... 73
Figure 11. Bit Synchronizer Description ...................................................................................................................... 27
Figure 12. FEI Process ................................................................................................................................................ 28
Figure 13. Optimized Afc (AfcLowBetaOn=1) .............................................................................................................. 29
Figure 14. Temperature Sensor Response ................................................................................................................. 30
Figure 15. Rx Startup - No AGC, no AFC .................................................................................................................... 32
Figure 16. Rx Startup - AGC, no AFC ......................................................................................................................... 32
Figure 17. Rx Startup - AGC and AFC ........................................................................................................................ 32
Figure 18. Listen Mode Sequence (no wanted signal is received) .............................................................................. 34
Figure 19. Listen Mode Sequence (wanted signal is received) ................................................................................... 36
Figure 20. Auto Modes of Packet Handler ................................................................................................................... 37
Figure 21. SX1239 Data Processing Conceptual View ............................................................................................... 38
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