Application Note AN-1136
Discrete Power Quad Flat No-Lead (PQFN)
Board Mounting Application Note
Table of Contents
Page
Introduction .............................................................2
Device construction ................................................2
Design considerations ............................................3
Assembly considerations ........................................4
Mechanical test results ...........................................7
Appendix A Model-specific data .............................9
Appendix A.1 2x2 Single devices ........................ 10
Appendix A.2 2x2 Dual devices........................... 11
Appendix A.3 3x3 A devices................................ 12
Appendix A.4 3.3x3.3 Single A devices .............. 13
Appendix A.5 3.3x3.3 Single B devices .............. 14
Appendix A.6 3.3x3.3 Dual devices .................... 15
Appendix A.7 4x5 Dual devices........................... 16
Appendix A.8 5x6 A devices................................ 17
Appendix A.9 5x6 B devices................................ 18
Appendix A.10 5x6 C devices ............................. 19
Appendix A.11 5x6 E devices.............................. 20
Appendix A.12 5x6 F devices .............................. 21
Appendix A.13 5x6 G devices ............................. 22
Appendix A.14 5x6 H devices ............................. 23
Appendix A.15 5x6 Dual devices......................... 24
Appendix A.16 6x6 devices ................................. 25
The Discrete PQFN package family comprises efficient devices with a wide range of input voltages, all
of which are lead-free as indicated by the PbF suffix after the part number (for example,
IRFH5300PbF).
There are various sizes and outlines. The main text of this application note contains guidance applicable
to the whole range, while Appendix A contains device outlines, substrate layouts and stencil designs for
each device. For more detail about individual devices, refer to the relevant product data sheet and
package outline drawing. To simplify board mounting and improve reliability, International Rectifier
manufactures PQFN devices to exacting standards. These high standards have evolved through
evaluating many different materials and designs. Although such evaluations have yielded good results, the
recommendations in this application note may need to be adjusted to suit specific production environments.
Discrete PQFN Technology
www.irf.com
AN-1136
Version 16 (revision
history),
May 2015
Board Mounting Application Note
Page 1 of 25
Introduction
Power Quad Flat No-Lead (PQFN) is a surface mount
semiconductor technology designed primarily for
board-mounted power applications. It eliminates
unnecessary elements of packaging that contribute to
higher inductance and resistance, both thermal and
electrical, so that its power capabilities exceed those
of comparably sized packages.
Device construction
PQFN devices are surface mounted and use current
plastic-molding techniques with wire bond
interconnects, as shown in Figure 1.
Figure 1 Sectional view
The PQFN package family includes various sizes and
device outlines. The main text of this application note
contains guidance applicable to the whole range, while
Appendix A contains device outlines, substrate layouts
and stencil designs for each device.
All recommendations are based on PCB-mounted
devices that have been X-rayed and subjected to
detailed analysis of post-reflow alignment and design
feasibility. Devices with new outline designs, such as
IRFH7911PbF,
were subject to more extensive study,
including placement positions from ideal through
various degrees of skew to erroneous.
To simplify board mounting and improve reliability,
International Rectifier manufactures PQFN devices to
exacting standards. These high standards have
evolved through evaluating many different materials
and designs. Although such evaluations have yielded
good results, the recommendations in this application
note may need to be adjusted to suit specific
production environments.
For information about the SupIRBuck™ PQFN, refer
to
AN-1132
and
AN-1133.
Figure 2 Sample PQFN contact pad configuration
Figure 3 shows how PQFN devices are labeled. Part
number, batch number and date code are provided to
support product traceability. The position of Pin 1 is
indicated in two ways:
A dot on the top side (Figure 4).
A half-moon marking on the underside (Figure 5).
Figure 2 shows a sample contact configuration for a
PQFN device. Specific pad assignments are shown in
the data sheet for each product.
Figure 3 Device markings
Discrete PQFN Technology
www.irf.com
AN-1136
Version 16 (revision
history),
May 2015
Board Mounting Application Note
Page 2 of 25
If pad numbering is required to produce a component
outline in the library of a CAD system, International
Rectifier recommends that the conventions shown in
Figure 6 are adopted. This makes it easier to discuss
any issues that may arise during design and assembly.
Pin
1
2
Name
Source
Source
Source
Gate
Drain
Drain
Drain
Drain
Figure 4 Pin 1 indicator on an IRFH5300PbF
3
4
5
6
7
8
Figure 6 Recommended pad numbering
PQFN devices can be placed in parallel using simple
layouts (Figure 7). International Rectifier recommends a
minimum separation of 0.500mm (0.020"). The separation
can be adjusted to reflect local process capabilities but
should allow for rework. Micro-screen design and
desoldering tool type may affect how closely devices
are placed to each other and to other components.
Figure 5 Pin 1 indicator on an IRFH5300PbF
Design considerations
Substrates
The PQFN was originally developed and evaluated for
use with epoxy glass-woven substrates (FR-4). The
test substrates were finished in Organic Solderability
Preservative (OSP), but any of the numerous surface
finishes available are suitable.
The substrate finish can affect the amount of energy
required to make solder joints; this can in turn be a
factor in solder quality issues such as solder balling,
tombstoning (or tilt) and the formation of voids.
Substrate designs
To achieve low-loss track layouts, PQFN devices were
designed for use with layouts that use solder-mask-
defined (SMD) pad lands and non-solder-mask-
defined (NSMD) lead lands. The devices were also
evaluated with entirely NSMD layouts. The device
outlines and the use of solder-mask-defined pads
contribute to efficient substrate design. Large-area
tracks optimize electrical and thermal performance.
Figure 7 Placing PQFN devices in parallel
Refer to Appendix A for device outlines, substrate
layouts and stencil designs for each package size and
device outline in the PQFN range.
Discrete PQFN Technology
www.irf.com
AN-1136
Version 16 (revision
history),
May 2015
Board Mounting Application Note
Page 3 of 25
Assembly considerations
International Rectifier designed PQFN devices to be
as easy as possible to assemble using standard
surface mounting techniques. However, procedures
and conditions can have a profound influence on
assembly quality. It is therefore necessary to develop
an effective process based on the individual
requirements for the application.
Packaging
PQFN devices are supplied in tape and reel format
(Figure 8).
The package labeling shows whether devices should
be treated as Moisture Sensitivity Level (MSL) 1, 2 or 3
after a bag has been opened. Appropriate storage is
important to guarantee good solderability.
International Rectifier recommends that, when not in
use, reels of devices should be resealed into the
protective bags in which they were supplied.
Solder pastes
International Rectifier evaluated different types of solder
paste from various manufacturers. The properties of
pastes vary from manufacturer to manufacturer, meaning
that some perform better than others. In general, high
slumping pastes tend to suffer more from solder balling
than slump-resistant pastes. In addition, some pastes
appear to be more prone to voiding than others.
Solder alloys, metal contents and flux constituents all
influence the rheology of the solder paste. This in turn
influences how the paste reacts during processing.
The assembly and board-level reliability of the PQFN
package have only been evaluated using lead-free
pastes (Sn96.5 Ag3.0 Cu0.5).
Evaluations of lead-free devices used a reflow profile
that conforms to IPC/JEDEC standard J STD 020C
(July 2004 revision). As devices may be subjected to
multiple reflows when PCBs are double-sided or
reworked, the evaluations used up to three reflows.
International Rectifier recommends that customers
should conform to J STD 020C in setting reflow
profiles and should not exceed three reflows.
Stencil design
The stencil design is instrumental in controlling the
quality of the solder joint. Appendix A shows stencil
designs that have given good results with the
recommended substrate outlines. These are based on
reductions of 25% for the pad lands and 20% for the
lead lands, which is equivalent to printing 75% and
80% of the area respectively using a stencil thickness
of 0.127mm (0.005"). The design should be revised for
other stencil thicknesses.
Stencils for PQFN can be used with thicknesses of
0.100-0.250mm (0.004-0.010"). Stencils thinner than
0.100mm are unsuitable because they deposit
insufficient solder paste to make good solder joints
with the ground pad; high reductions sometimes
create similar problems. Stencils in the range of
0.125mm-0.200mm (0.005-0.008"), with suitable
reductions, give the best results.
Dimensions (mm)
A
2X2
3X3
3.3X3.3
4X5
5X6
6X6
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
3.90
4.10
7.90
8.10
7.90
8.10
7.90
8.10
7.90
8.10
11.90
12.10
B
3.90
4.10
C
7.90
8.30
D
3.45
3.55
5.40
5.60
5.45
5.55
5.40
5.60
5.40
5.60
7.40
7.60
E
2.20
2.30
3.20
3.40
3.50
3.70
5.20
5.40
6.20
6.40
6.20
6.40
F
2.20
2.30
3.20
3.40
3.50
3.70
4.20
4.40
5.20
5.40
6.20
6.40
G
0.55
0.65
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
1.50
H
1.50
1.60
1.50
1.60
1.50
1.60
1.50
1.60
1.50
1.60
1.50
1.60
3.90 11.70
4.10 12.30
3.90 11.70
4.10 12.30
3.90 11.70
4.10 12.30
3.90 11.90
4.10 12.10
3.90 15.70
4.10 16.30
Figure 8 Tape and reel packaging
Storage requirements
PQFN devices are packed in sealed, nitrogen-purged,
antistatic bags. The sealed bags provide adequate
protection against normal light levels but it is prudent
to avoid prolonged exposure to bright light sources.
The bags also provide protection from the ambient
atmosphere. Devices in sealed, unopened bags have
a shelf life of one year.
Discrete PQFN Technology
www.irf.com
AN-1136
Version 16 (revision
history),
May 2015
Board Mounting Application Note
Page 4 of 25
Post-reflow evaluations can help to assess how a stencil
is performing within a given process. Two main problem
areas can be addressed by improving stencil design:
Solder balling around the perimeter of the die.
This can be caused by too much solder paste, in
which case the stencil might need to be reduced
by more than 25%. The reduction can be
symmetrical but biasing it unevenly may help to
prevent solder balling; the stencil designs in
Appendix A have apertures moved further from the
die edge for this reason. Solder balling can result
from other external factors, such as the moisture
content of the board and incorrect ramp rates or
insufficient soak times in the reflow profile.
Leadless packages like PQFN can sometime
accentuate existing deficiencies within a process.
Misshapen joints.
If the joints are smaller or seem
to be only partially made, this might suggest that
there is insufficient solder to make the joint. If,
however, the joints have what appear to be
additional areas extending from their edges, they are
usually the result of too much solder; this is almost
certainly the case if solder balls are also present.
Insufficient solder can also cause voiding but this
is more likely to arise from other factors, including
surface finish, solder paste and substrate condition.
There are no special requirements for successful
assembly, but all reflow processes used in evaluation
and qualification complied with the recommendations of
solder paste suppliers. Using incorrect reflow profiles
can cause solder quality issues such as solder balling,
tombstoning (or tilt) and the formation of voids; if such
problems arise, the reflow profile should be checked.
The PQFN package is designed to have superior
thermal resistance properties. For this reason, it is
essential that the core of the substrate reaches
thermal equilibrium during the pre-heating stage of the
reflow profile to ensure that adequate thermal energy
reaches the solder joint.
Inspection
For comprehensive information on inspecting board-
mounted PQFN devices, refer to the PQFN Inspection
Application Note (AN-1154).
As with all QFN packaging, the best way to inspect
devices after reflow is through a combination of visual
inspection of the peripheral solder joints and X-ray
imaging of the connections directly under the package.
Device placement
Inaccurate placement may result in poor solder joints
or in devices being tilted and/or misaligned. Ideally,
PQFN devices should be placed to an accuracy of
0.050mm on both X and Y axes but, during
evaluations, devices centered themselves from
placement inaccuracies of more than 0.300mm. Self-
centering behavior is highly dependent on solders and
processes, and experiments should be run to confirm
the limits of self-centering on specific processes.
Reflow equipment
PQFN devices are suitable for assembly using surface
mount technology reflowing equipment and are
recommended for use with convection, vapor phase
and infrared equipment. PbF qualified devices have a
good resistance to short-term exposure to high
temperatures, making them suitable for reflow profiles
of up to 260°C (measured by attaching a
thermocouple to a PQFN device).
Figure 9 X-rays of PQFN
Figure 9 is a typical X-ray image of a board-mounted
PQFN device, which shows the solder joints, device
alignment and solder voiding level. Regarding solder
joint voiding, most customers use 25–30% as the
acceptable limit, often citing industry standards such
as IPC-A-610 or IPC-7093. However, having tested
board-mounted devices deliberately voided up to 45%,
International Rectifier has been unable to detect any
deterioration in electrical or thermal performance in
application compared with devices voided to 5–10%.
Discrete PQFN Technology
www.irf.com
AN-1136
Version 16 (revision
history),
May 2015
Board Mounting Application Note
Page 5 of 25
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
