HS-82C08RH
TM
Data Sheet
August 2000
File Number
3040.3
Radiation Hardened 8-Bit Bus Transceiver
The Intersil HS-82C08RH is a radiation-hardened octal bus
transceiver with three-state outputs. It is manufactured using
a self-aligned, junction isolated CMOS process and is
designed for use with the HS-80C08RH radiation-hardened
microprocessor. The HS-82C08RH allows asynchronous
two-way communication between data buses. The direction
of data flow is determined by the logic level on the
transmit/receive (T/R) input. A logic high on the T/R input
specifies data flow from Port A to Port B of the device.
Conversely, a logic low on the T/R input specifies data flow
from Port B to Port A. The Output Enable input disables both
ports by placing them in the high impedance state.
The HS-82C08RH is ideally suited for a wide variety of
buffering applications in radiation-hardened microcomputer
systems.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95714. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Features
• Electrically Screened to SMD # 5962-95714
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Performance
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
- Latch-Up Immune EPI-CMOS . . . . . >1 x 10
12
rad(Si)/s
• Bidirectional Three-State Input/Outputs
• Low Propagation Delay Time
• Low Power Consumption
• Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V
• Electrically Equivalent to Sandia SA2997
• Military Temperature Range . . . . . . . . . . . -55
o
C to 125
o
C
Ordering Information
ORDERING NUMBER
5962R9571401QRC
5962R9571401QXC
5962R9571401VRC
5962R9571401VXC
INTERNAL
MKT. NUMBER
HS1-82C08RH-8
HS9-82C08RH-8
HS1-82C08RH-Q
HS9-82C08RH-Q
TRUTH TABLE
INPUTS
OPERATION
TRANSMIT
/RECEIVE
0
1
X
PORT A
Out
In
High Z
PORT B
In
Out
High Z
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Functional Diagram
A0
B0
OUTPUT
ENABLE
0
A1
A2
A3
PORT A4
A
A5
A6
A7
B1
B2
B3
B4 PORT
B
B5
B6
B7
0
1
X = Don’t Care
T/R
OE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil and Design is a trademark of Intersil Corporation.
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Copyright © Intersil Corporation 2000
HS-82C08RH
Pinouts
20 LEAD CERAMIC DUAL-IN-LINEMETAL-SEAL PACKAGE
(SBDIP) MIL-STD-1835, CDIP2-T20
TOP VIEW
A0
A1
A2
A3
A4
A5
A6
A7
OE
1
2
3
4
5
6
7
8
9
20 V
DD
19 B0
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 T/R
20 LEAD CERAMIC METAL SEALFLATPACK PACKAGE
(FLATPACK) MIL-STD-1835, CDFP4-F20
TOP VIEW
A0
A1
A2
A3
A4
A5
A6
A7
OE
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
B0
B1
B2
B3
B4
B5
B6
B7
T/R
GND 10
PIN
A0-A7
B0-B7
DESCRIPTION
Local Bus Data I/O Pins
System Bus Data I/O Pins
PIN
T/R
OE
DESCRIPTION
Transmit/Receive Input
Active Low Output Enable
Logic Diagram
A0
1
TSB
TSB
A1
2
TSB
TSB
A2
3
TSB
TSB
A3
4
TSB
TSB
A4
5
TSB
TSB
A5
OE 9
6
B ENABLE
A6
T/R11
A7
8
7
A ENABLE
TSB
TSB
TSB
TSB
12
B7
TSB
TSB
13
B6
14
B5
15
B4
16
B3
17
B2
18
B1
19
B0
NOTE: An Important caveat that is applicable to CMOS devices in general is that unused inputs should never be left floating. This rule applies to
inputs connected to a three-state bus. The need for external pull-up resistors during three-state bus conditions is eliminated by the presence of
regenerative latches on the following HS-82C08RH pins. A0-7 and B0-7 The functional block diagram depicts one of these pins with the regenerative
latch. When the CMOS driver assumes the high impedance state, the latch holds the bus in whatever logic state (high or low) it was before the three-
state condition. A transient drive current of
±1.5mA
at V
DD
/2
±0.5V
for 10ns is required to switch the latch. Thus, CMOS device inputs connected to
the bus are not allowed to float during three-state conditions.
2
HS-82C08RH
Die Characteristics
DIE DIMENSIONS:
76.0 mils x 89.4 mils x 14 mils
±1
mil
INTERFACE MATERIALS:
Glassivation:
Type: SiO
2
Thickness: 8k
Å
±1k
Å
Top Metallization:
Type: Si - Al
Thickness: 11k
Å
±2k
Å
Metallization Mask Layout
HS-82C08RH
(20) V
DD
(1) A0
(19) B0
A1 (2)
(18) B1
A2 (3)
(17) B2
A3 (4)
(16) B3
A4 (5)
(15) B4
A5 (6)
(14) B5
A6 (7)
(13) B6
A7 (8)
GND (10)
T/R (9)
OE (9)
(12) B7
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
www.intersil.com
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