DSC591-03
Crystal-less
TM
Clock Generator
for Baseboard Management Controller (BMC)
General Description
The DSC591-03 is a two output Crystal-less
TM
clock generator.
It implements Discera’s
proven silicon MEMS technology to provide
excellent jitter, stability and reliability. The
device incorporates features useful in servers
and other applications that employ the
Baseboard Management Controller (BMC),
such as the ability for the two LVCMOS
outputs to drive up to four loads. Three pins
are dedicated for selecting various drive
strengths per LVCMOS output. Independent
drive strength control facilitates signal
integrity optimization as well as the reduction
in EMI and power supply ripple noise.
The DSC591-03 is packaged in a 14-pin
3.2x2.5 mm QFN package and available in
temperature
grades
from
extended
commercial to automotive.
Preliminary Datasheet
Features
Two LVCMOS Clocks
o
One fixed 50MHz
o
One pin-selectable 50MHz or 25MHz
Pin-Selectable Output Drive Strength
o
Three pins = 8 settings per output
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o
Automotive: -55° to 125° C
o
Ext. Industrial: -40° to 105° C
o
Industrial: -40° to 85° C
o
Ext. Commercial: -20° to 70° C
Short Lead Times: 2 Weeks
Miniature 3.2x2.5mm Footprint
Excellent Shock & Vibration Immunity
o
Qualified to MIL-STD-883
High Reliability
o
20x better MTBF than quartz oscillators
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Block Diagram
Applications
Servers
Workstations
High End Motherboards
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DSC591-03
Page 1
MKQBPD13040101-1.8
DSC591-03
Low-Jitter Configurable Dual CMOS Oscillator
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
OE
NC
C0S0
VSS
C0S1
C0S2
FS
CLK1
C1S0
C1S1
CLK0
VDD0*
VDD
C1S2
Pin Type
I
NA
I
Power
I
I
I
O
I
I
O
Power
Power
I
Description
Enables outputs when high (default) and disables when low
Leave unconnected or grounded
Least significant bit for drive strength selection for CLK0. Pin has
an internal Pull-up
Ground
Middle bit for drive strength selection for CLK0. Pin has an
internal Pull-up
Most significant bit for drive strength selection for CLK0. Pin has
an internal Pull-up
Frequency select
LOW: CLK1 = 25MHz
HIGH: CLK1 = 50MHz (Default)
Pin has an internal Pull-up
LVCMOS output 1
Least significant bit for drive strength selection for CLK1. Pin has
an internal Pull-up
Middle bit for drive strength selection for CLK1. Pin has an
internal Pull-up
LVCMOS output 0
Power Supply for CLK0
Power Supply
Most significant bit for drive strength selection for CLK1. Pin has
an internal Pull-up
*VDD0 must be less than or equal to VDD
Pin Diagram
Connection Diagram
Layout Guideline
(mm [inch])
*Optional matching resistor Ropt = 22-33Ω
*Pins 3,5,6,7,9,10 & 14 have an internal
pullup resistor
*Connect the center pad to VSS for
best thermal performance
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DSC591-03
Page 2
MKQBPD13040101-1.8
DSC591-03
Low-Jitter Configurable Dual CMOS Oscillator
Operational Description
The DSC591-03 is a BMC clock generator
consisting of a MEMS resonator and a support
PLL IC.
The device features two CMOS
outputs, dual 50MHz or 50 and 25MHz, as
chosen by the frequency select (FS) pin 7. See
Table 2. There is also independent control of
the output voltage levels. The high voltage
level of CLK1 is equal to the main supply
voltage, VDD (pin 13). VDD0 (pin 12) sets
the high voltage level of CLK0. VDD0 must be
equal to or less than VDD at all times to
insure proper operation. VDD0 can be as low
as 1.65V.
When Enable (pin 1) is floated or connected to
VDD, the DSC591-03 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
The DSC591-03 features programmable drive
strength for each output. Using six control
pins (C0S[2:0] & C1S[2:0]), output drive
strength can be adjusted to match circuit
board impedances to reduce power supply
noise, overshoot/undershoot and EMI. Table
1 displays typical drive levels at VDD=3.6V
and room temperature.
Table 1. Drive level vs. CXS[2:0]
Output Drive Strength Bits
[CXS2, CXS1, CXS0]
Default [0x111b]
0x000b
0x001b
0x010b
0x011b
0x100b
0x101b
0x110b
0x111b
I
oh
(mA)
5.4
8.4
10.5
12.0
13.2
14.1
14.8
15.4
I
ol
(mA)
4.9
6.4
8.0
9.5
10.9
12.4
13.8
15.2
Table 2. Frequency Selection
FS
0
1
CLK0 (MHz)
50
50
CLK1 (MHz)
25
50
Output Waveform: CMOS
t
R
V
OH
t
F
Output
V
OL
1/f
o
t
DA
V
IH
t
EN
Enable
V
IL
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DSC591-03
Page 3
MKQBPD13040101-1.8
DSC591-03
Low-Jitter Configurable Dual CMOS Oscillator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
Condition
40sec max.
Note: 1000+ years of data retention on internal memory
Specifications
Parameter
Supply Voltage
1
Supply Voltage
Supply Current
Supply Current
2
Frequency Stability
Aging
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
(Unless specified otherwise: T=25° C, max CMOS drive strength)
Condition
V
DD
V
DD0
I
DD
I
DD
∆f
∆f
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up exists on all digital IO
V
DD0
<= V
DD
EN pin low – outputs are disabled
EN pin high – outputs are enabled
C
L
=15pF, F
C1
=F
C2
=50 MHz
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
Min.
2.25
1.65
Typ.
Max.
3.6
3.6
23
Unit
V
V
mA
mA
21
32
±10
±25
±50
±5
5
0.75xV
DD
-
-
0.25xV
DD
5
20
40
ppm
ppm
ms
V
ns
ns
kΩ
CMOS Outputs
Output Logic Levels
Output logic high
Output logic low
Output Transition time
4
Rise Time
Fall Time
Output Duty Cycle
Period Jitter
5
V
OH
V
OL
t
R
t
F
SYM
J
PER
I=±6mA
CXS [2:0] = 0x111b
20% to 80%
C
L
=15pf
45
F
C1
=F
C2
=50 MHz
3
0.9xV
DD
-
1.1
1.4
-
0.1xV
DD
2
2
55
V
ns
%
ps
RMS
Notes:
1. Pins 12 and 13 (V
DD
& V
DD0
) should be filtered with a 0.01uf capacitor.
2. Output is enabled if Enable pad is floated or not connected.
3. t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
4. Output Waveform and Test Circuit figures above define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
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DSC591-03
Page 4
MKQBPD13040101-1.8
DSC591-03
Low-Jitter Configurable Dual CMOS Oscillator
Drive Level vs. CXS[2:0]
I
oh
vs. CXS[2:0]
VDD=3.6V
18
16
14
12
10
8
6
4
2
0
18
16
14
12
10
8
6
4
2
0
I
ol
vs. CXS[2:0]
VDD=3.6V
Ioh (mA)
Iol (mA)
25C
‐40C
85C
25C
‐40C
85C
I
oh
vs. CXS[2:0]
VDD = 2.25V
10
9
8
7
6
5
4
3
2
1
0
12
10
Iol (mA)
8
6
4
2
0
I
ol
vs. CXS[2:0]
VDD = 2.25V
Ioh (mA)
25C
‐40C
85C
25C
‐40C
85C
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DSC591-03
Page 5
MKQBPD13040101-1.8
嵌入式系统
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