DSC2010
Low-Jitter Configurable CMOS Oscillator
General Description
The DSC2010 series of high performance
CMOS oscillators utilize a proven silicon
MEMS technology to provide excellent jitter
and stability while incorporating additional
device functionality. The DSC2010 allows
the user to easily modify the frequency and
drive strength of the oscillator using pins.
The DSC2010 has provision for up to four
user-defined pre-programmed, pin-selectable
output frequencies, and eight pin-selectable
output drive levels to help reduce EMI.
DSC2010 is packaged in a 14-pin 3.2x2.5
mm
QFN
package
and
available
in
temperature grades from Ext. Commercial to
Automotive.
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o
Automotive: -55° to 125° C
o
Ext. Industrial: -40° to 105° C
o
Industrial: -40° to 85° C
o
Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Pin-Selectable Configurations
o
3-bit Output Drive Strength
o
2-bit Output Frequency Combinations
Short Lead Times: 2 Weeks
Wide Freq. Range:
o
CMOS Output: 2.3 to 170 MHz
Miniature Footprint of 3.2x2.5mm
Excellent Shock & Vibration Immunity
o
Qualified to MIL-STD-883
High Reliability
o
20x better MTF than quartz oscillators
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Block Diagram
Applications
Consumer Electronics
Storage Area Networks
o
SATA, SAS, Fibre Channel
Passive Optical Networks
o
EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o
1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
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DSC2010
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MK-Q-B-P-D-12042601-2
DSC2010
Low-Jitter Configurable CMOS Oscillator
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
NC
GND
FS0
FS1
NC
Output
OS0
OS1
NC
VDD2
VDD
OS2
Pin Type
I
NA
NA
Power
I
I
NA
O
I
I
NA
Power
Power
I
Description
Enables outputs when high and disables when low
Leave unconnected or grounded
Leave unconnected or grounded
Ground
Least significant bit for frequency selection
Most significant bit for frequency selection
Leave unconnected or grounded
CMOS output
Least significant bit for output drive strength selection
Middle bit for output drive strength selection
Leave unconnected or grounded
Power Supply
Power Supply
Most significant bit for output drive strength selection
Operational Description
The DSC2010 is a CMOS oscillator consisting
of a MEMS resonator and a support PLL IC.
The CMOS output is generated through
independent 8-bit programmable dividers from
the output of the internal PLL.
The actual frequency output by the DSC2010
is controlled by an internal pre-programmed
memory (OTP).
This memory stores all
coefficients required by the PLL for up to four
different frequencies. Two control pins (FS0 –
FS1) select the output frequency. Discera
supports customer defined versions of the
DSC2010. Standard frequency options are
described in the following sections.
When Enable (pin 1) is floated or connected to
VDD, the DSC2010 is in operational mode.
Driving Enable to ground will disable the
output driver (
hi-impedance
mode).
The DSC2010 has programmable output drive
strength. Using three control pins (OS0-OS2)
the drive strength can be adjusted to match
circuit board impedances to reduce power
supply noise, overshoot/undershoot and EMI.
Table 1 displays typical rise / fall times for the
output with a 15pf load capacitance as a
function of these control pins at VDD=3.3V
and room temperature.
Table 1. Rise/Fall times for drive strengths
Output Drive Strength Bits
[OS2, OS1, OS0] - Default [111]
000
001
010
011
100
101
110
111
tr
tf
(ns)
(ns)
2.1
2.5
1.7
2.4
1.6
2.4
1.4
2.2
1.3
1.8
1.3
1.6
1.2
1.4
1.1
1.4
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DSC2010
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MK-Q-B-P-D-12042601-2
DSC2010
Low-Jitter Configurable CMOS Oscillator
Output Clock Frequencies
Table 2 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code. Customer defined combinations are available.
Table 2. Pre-programmed pin-selectable output frequency combinations
Ordering
Info
A0001
A0002
A0003
A0004
A0005
A0006
A0007
A0008
A0009
A00010
A000X
Freq
(MHz)
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
Freq Select Bits [FS1, FS0] –
Default is [11]
00
27
155.52
25
72
27
16
96
25
55.296
27.648
01
24
106.25
75
74.25
50
13.56
55
50
27.648
55.296
10
148.5
156.25
125
36
0*
0*
0*
0*
0*
0*
11
74.25
125
150
108
0*
0*
0*
0*
0*
0*
Contact factory for additional configurations.
Frequency select bit are weakly tied high so if left unconnected the default setting will be [11] and
the device will output the associated frequency highlighted in
Bold.
0* – denotes invalid selection, output frequency is not specified.
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DSC2010
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MK-Q-B-P-D-12042601-2
DSC2010
Low-Jitter Configurable CMOS Oscillator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Ordering Code
Condition
Temp Range
E: -20 to 70
I: -40 to 85
L: -40 to 105
M: -55 to 125
Packing
T: Tape & Reel
: Tube
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
40sec max.
DSC2010
F I 2
-
xxxxx
T
Freq (MHz)
See Freq. table
Package
F: 3.2x2.5mm
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Note: 1000+ years of data retention on internal memory
Specifications
(Unless specified otherwise: T=25° C, max CMOS drive strength)
Parameter
Supply Voltage
1
Supply Current
Frequency Stability
Aging
Startup Time
2
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
3
Output Enable Time
Pull-Up Resistor
4
V
DD
I
DD
Δf
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up exists on all digital IO
40
EN pin low – output is disabled
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
0.75xV
DD
-
Condition
Min.
2.25
Typ.
21
Max.
3.6
23
±10
±25
±50
±5
5
-
0.25xV
DD
5
20
Unit
V
mA
ppm
ppm
ms
V
ns
ns
kΩ
CMOS Output
Supply Current
4
Output Logic Levels
Output logic high
Output logic low
Output Transition time
3
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
Integrated Phase Noise
Notes:
1.
2.
3.
4.
I
DD
V
OH
V
OL
t
R
t
F
f
0
SYM
J
PER
J
CC
EN pin high – output is enabled
C
L
=15pF, F
O
=125 MHz
I=±6mA
20% to 80%
C
L
=15pf
Commercial/Industrial temp range
Automotive temp range
F
O
=125 MHz
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
2.3
45
0.9xV
DD
-
31
35
-
0.1xV
DD
mA
V
1.1
1.3
2
2
170
100
55
ns
MHz
%
ps
RMS
ps
RMS
3
0.3
0.38
1.7
2
Pin 4 V
DD
should be filtered with 0.01uf capacitor.
t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Output is enabled if Enable pad is floated or not connected.
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DSC2010
Page 4
MK-Q-B-P-D-12042601-2
DSC2010
Low-Jitter Configurable CMOS Oscillator
Nominal Performance Parameters
(Unless specified otherwise: T=25° C, V
DD
=3.3 V)
2.5
25MHz-CMOS
Phase Jitter (ps RMS)
2.0
50MHz-CMOS
106MHz-CMOS
125MHz-CMOS
1.5
1.0
0.5
0.0
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
Output Waveform: CMOS
t
R
V
OH
CMOS Phase jitter (integrated phase noise)
t
F
Output
V
OL
1/f
o
t
DA
V
IH
t
EN
Enable
V
IL
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DSC2010
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MK-Q-B-P-D-12042601-2
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