HI-3585, HI-3586
July 2013
ARINC 429
Terminal IC with SPI Interface
FEATURES
·
·
·
·
·
·
·
·
·
·
·
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ARINC specification 429 compliant
3.3V or 5.0V logic supply operation
On-chip analog line driver and receiver connect
directly to ARINC 429 bus
Programmable label recognition for 256 labels
32 x 32 Receive FIFO and 32 x 32 Transmit FIFO
Independent data rates for Transmit and Receive
High-speed, four-wire Serial Peripheral Interface
Label bit-order control
32nd transmit bit can be data or parity
Self test mode
Low power
Industrial & extended temperature ranges
GENERAL DESCRIPTION
The HI-3585 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a Serial Peripheral Interface
(SPI) enabled microcontroller to the ARINC 429 serial bus.
The device provides one receiver with user-programmable
label recognition for any combination of 256 possible
labels, 32 x 32 Receive FIFO and analog line receiver.
The independent transmitter has a 32 x 32 Transmit FIFO
and built-in line driver. The status of the transmit and
receive FIFOs can be monitored using the programmable
external interrupt pin, or by polling the HI-3585 Status
Register. Other features include a programmable option
of data or parity in the 32nd bit, and the ability to switch the
bit-signifiance of ARINC 429 labels. Pins are available
with different input resistance and output resistance
values which provides flexibility when using external
lightning protection circuitry.
The Serial Peripheral Interface minimizes the number of
host interface signals resulting in a small footprint device
that can be interfaced to a wide range of industry-standard
microcontrollers supporting SPI. Alternatively, the SPI
signals may be controlled using just four general purpose
I/O port pins from a microcontroller or custom FPGA. The
SPI and all control signals are CMOS and TTL compatible
and support 3.3V or 5V operation.
The HI-3585 applies the ARINC 429 protocol to the
receiver and transmitter. ARINC 429 databus timing
comes from a 1 MHz clock input, or an internal counter can
derive it from higher clock frequencies having certain fixed
values, possibly the external host processor clock.
The HI-3586 is functionally identical to the HI-3585 except
it includes digital transmitter output pins 429D1 and 429D0
instead of a built-in line driver. This allows the designer to
take advantage of Holt’s single supply rail line drivers,
such as the 5V HI-8592 or 3.3V HI-8596.
PIN CONFIGURATIONS
(Top View)
N/C
RINA
RINA-40
N/C
VDD
N/C
V+
N/C
AOUT27
AOUT37
N/C
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
-
-
-
-
-
-
-
-
-
-
-
N/C
RINB-40
RINB
N/C
N/C
N/C
MR
SI
CS
N/C
N/C
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
- 11
HI-3585PCI
HI-3585PCT
-
-
-
-
-
-
-
-
-
-
-
BOUT27
BOUT37
N/C
V-
N/C
TFLAG
N/C
N/C
RFLAG
N/C
N/C
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
(DS3585 Rev. J)
HOLT INTEGRATED CIRCUITS
www.holtic.com
N/C
N/C
N/C
SCK
N/C
GND
N/C
ACLK
SO
N/C
N/C
-
-
-
-
-
-
-
-
-
-
-
12
13
14
15
16
17
18
19
20
21
22
07/13
HI-3585, HI-3586
BLOCK DIAGRAM
VDD
ARINC 429
Line Driver
(HI-3585 only)
V+
10 Ohm
ACLK
ARINC
Clock
Divider
ARINC 429
Transmit
Data FIFO
ARINC 429
Transmit
Formatter
AOUT37
AOUT27
BOUT27
27 Ohm
27 Ohm
10 Ohm
BOUT37
V-
429D1(HI-3586 only)
SCK
CS
SI
SO
Control Register
Status Register
Label
Filter
Bit Map
Memory
SPI
Interface
429D0 (HI-3586 only)
TFLAG
RINA-40
RINB-40
RINA
RINB
40 Kohm
40 Kohm
ARINC 429
Line Receiver
ARINC 429
Valid word
Checker
Label
Filter
ARINC 429
Received
Data FIFO
RFLAG
GND
PIN DESCRIPTIONS
SIGNAL FUNCTION
RINB
RINB-40
MR
SI
CS
SCK
GND
ACLK
SO
RFLAG
TFLAG
V-
BOUT37
BOUT27
AOUT27
AOUT37
V+
VDD
RINA-40
RINA
429D1
429D0
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
POWER
INPUT
OUTPUT
OUTPUT
OUTPUT
POWER
OUTPUT
OUTPUT
OUTPUT
OUTPUT
POWER
POWER
INPUT
INPUT
OUTPUT
OUTPUT
DESCRIPTION
ARINC receiver negative input. Direct connection to ARINC 429 bus
Alternate ARINC receiver negative input. Requires external 40K ohm resistor
Master Reset. A positive pulse clears Receive and Transmit data FIFOs and flags
SPI interface serial data input
Chip select. Data is shifted into SI and out of SO when CS is low.
SPI Clock. Data is shifted into or out of the SPI interface using SCK
Chip 0V supply
Master timing source for the ARINC 429 receiver and transmitter
SPI interface serial data output
Goes high when ARINC 429 Receive FIFO is empty (CR15=0), or full (CR15=1)
Goes high when ARINC 429 Transmit FIFO is empty (CR14=0), or full (CR14=1)
Minus 5V power supply to ARINC 429 Line Driver
ARINC line driver negative output. Direct connection to ARINC 429 bus
Alternate ARINC line driver negative output. Requires external 10 ohm resistor
Alternate ARINC line driver positive output. Requires external 10 ohm resistor
ARINC line driver positive output. Direct connection to ARINC 429 bus
Positive 5V power supply to ARINC 429 Line Driver
3.3V or 5.0V logic power
Alternate ARINC receiver positive input. Requires external 40K ohm resistor
ARINC receiver positive input. Direct connection to ARINC 429 bus
Digital positive output to external line driver
Digital negative output to external line driver
NOTE
10K ohm pull-down*
10K ohm pull-down*
10K ohm pull-up*
10K ohm pull-down*
10K ohm pull-down*
(HI-3585 only)
(HI-3585 only)
(HI-3585 only)
(HI-3585 only)
(HI-3585 only)
(HI-3585 only)
(HI-3586 only)
(HI-3586 only)
* Internal Pull-up or Pull-down
HOLT INTEGRATED CIRCUITS
2
HI-3585, HI-3586
INSTRUCTIONS
Instruction op codes are used to read, write and configure the HI-
3585. When CS goes low, the next 8 clocks at the SCK pin shift an
instruction op code into the decoder, starting with the first positive
edge. The op code is fed into the SI pin most significant bit first.
For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies
depending on word type written: 16-bit writes to Control Register,
32-bit ARINC word writes to transmit FIFO or 256-bit writes to the
label-matching enable/disable table.
Table 1 lists all instructions. Instructions that perform a reset or set,
or enable transmission are executed after the last SI bit is received
while CS is still low.
Example:
CS
SCK
SI
op code 07hex
MSB
one SPI Instruction
For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into
the decoder, at the next falling SCK edge. As with write
instructions, data field bit-length varies with read instruction type.
data field 02hex
LSB MSB
LSB
TABLE 1. DEFINED INSTRUCTION OP CODES
OP CODE
Hex
DATA FIELD
DESCRIPTION
00
01
02
03
04
05
06
None
None
None
None
8 bits
8 bits
256 bits
No instruction implemented
After the 8th op code bit is received, perform Master Reset (MR)
After the 8th op code bit is received, reset all label selections
After the 8th op code bit is received, set all the label selections
Reset the label at the address specified in the data field
Set the label at the address specified in the data field
Starting with label FF hex, consecutively set or reset each label in descending order
For example, a Data Field pattern starting with 1011 will set labels FF, FD, and FC
hex and reset label FE hex
Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control
Register bit CR1 is set, the ARINC receiver and transmitter operate from the divided ACLK clock.
Allowable values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value
results in no clock. Note: ACLK input frequency and division ratio must yield 1 MHz clock.
Read the next word in the Receive FIFO. If the FIFO is empty, it will read zeros
No Instruction Implemented
Read the Status Register
Read the Control Register
Read the ACLK divide value programmed previously using op code 07 hex
Read the Label look-up memory table consecutively starting with address FF hex.
Write up to 32 words into the next empty positions of the Transmit FIFO
No instruction implemented
Write the Control Register
Reset the Transmit FIFO. After the 8th op code bit is received, the transmit FIFO will be empty
Transmission enabled by this instruction only if Control Register bit 13 is zero
07
8 bits
08
09
0A
0B
0C
0D
0E
0F
10
11
12
32 bits
None
8 bits
16 bits
8 bits
256 bits
N x 32 Bits
None
16 bits
None
None
HOLT INTEGRATED CIRCUITS
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HI-3585, HI-3586
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-3585 contains a 16-bit Control Register which is used to
configure the device. Control Register bits CR15 - CR0 are loaded
from a 16-bit data value appended to SPI instruction 10 hex. The
Control Register contents may be read using SPI instruction 0B
hex. Each bit of the Control Register has the following function:
STATUS REGISTER
The HI-3585 contains an 8-bit Status Register which can be
interrogated to determine the status of the ARINC receiver, data
FIFOs and transmitter. The contents of the Status Register are
output using SPI instruction 0A hex. Unused bits are output as
Zeros. The following table defines the Status Register bits.
CR
Bit
Cr0
(LSB)
CR1
FUNCTION STATE
Receiver
Data Rate
Select
ARINC Clock
Source Select
0
1
0
1
DESCRIPTION
Data rate = CLK/10 (ARINC 429 High-Speed)
Data rate = CLK/80 (ARINC 429 Low-Speed)
ARINC CLK = ACLK input frequency
SR
Bit
SR0
(LSB)
FUNCTION
Receive FIFO
Empty
STATE
0
DESCRIPTION
Receiver FIFO contains valid data
Sets to One when all data has
been read. RFLAG pin reflects the
state of this bit when CR15=0
Receiver FIFO is empty
Receiver FIFO holds less than 16
words
Receiver FIFO holds at least 16
words
Receiver FIFO not full. RFLAG pin
reflects the state of this bit when
CR15=1
Receiver FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period
Transmit FIFO not empty.
Sets to One when all data has
been sent. TFLAG pin reflects the
state of this bit when CR14=0
Transmit FIFO is empty.
Transmit FIFO contains less than 16
words
Transmit FIFO contains at least 16
words
Transmit FIFO not full. TFLAG pin
reflects the state of this bit when
CR14=1
Transmit FIFO full.
Always “0”
Always “0”
1
ARINC CLK = ACLK divided by the value
programmed with SPI Instruction 07 hex
Label recognition disabled
1
1
Label recognition enabled
Transmitter 32nd bit is data
Transmitter 32nd bit is parity
Receiver parity check disabled
Receiver odd parity check enabled
The transmitter’s digital outputs are internally
connected to the receiver logic inputs
Normal operation
Receiver decoder disabled
ARINC bits 10 and 9 must match CR7 and CR8
If receiver decoder is enabled,
the ARINC bit 10 must match this bit
If receiver decoder is enabled,
the ARINC bit 9 must match this bit
Transmitter 32nd bit is Odd parity
Transmitter 32nd bit is Even parity
Data rate = CLK/10, O/P slope = 1.5us
Data rate = CLK/80, O/P slope = 10us
Label bit order reversed (See Table 2)
Label bit order same as transmitted /
received (See Table 2)
Line Driver enabled
Line Driver disabled (force outputs to Null state)
Start transmission by SPI
instruction12 hex
Transmit whenever data is available
in the Transmit FIFO
TFLAG goes high when transmit FIFO is empty
TFLAG goes high when transmit FIFO is full
RFLAG goes high when receive FIFO is empty
RFLAG goes high when receive FIFO is full
SR6
SR7
(MSB)
Not used
Not used
1
0
0
SR5
Transmit FIFO
Full
SR4
Transmit FIFO
Half Full
1
0
1
0
SR3
Transmit FIFO
Empty
0
1
SR2
Receive FIFO
Full
0
0
1
0
1
0
1
SR1
Receive FIFO
Half Full
0
CR2
Enable Label
Recognition
Transmitter
Parity Bit
Enable
Receiver
Parity Check
Enable
Self Test
0
CR3
CR4
CR5
CR6
Receiver
Decoder
-
-
Transmitter
Parity
Select
Transmitter
Data Rate
ARINC Label
Bit Order
0
1
CR7
CR8
CR9
-
-
0
1
0
1
CR10
CR11
0
1
CR12
Disable
Line Driver
Transmission
Enable Mode
0
1
CR13
0
1
CR14
TFLAG
Definition
RFLAG
Definition
0
1
CR15
(MSB)
0
1
HOLT INTEGRATED CIRCUITS
4
HI-3585, HI-3586
FUNCTIONAL DESCRIPTION (cont.)
ARINC 429 DATA FORMAT
Control Register bit CR11 controls how individual bits in the
received or transmitted ARINC word are mapped to the HI-3585 SPI
data word bits during data read or write operations. The following
table describes this mapping:
Table 2. SPI / ARINC bit-mapping
SPI
Order
1
2 - 22
31 - 11
23 24 25 26 27 28 29 30 31 32
10
9
1
2
3
4
5
6
7
8
RECEIVER LOGIC OPERATION
Figure 2 is a block diagram showing receiver logic.
BIT TIMING
The ARINC 429 specification defines the following timing toler-
ances for received data:
HIGH SPEED
100K BPS ± 1%
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
5 µsec ± 5%
LOW SPEED
12K -14.5K BPS
10 ± 5 µsec
10 ± 5 µsec
34.5 to 41.7 µsec
. ARINC bit 32
Label (MSB)
CR11=0
Data
Label (LSB)
Parity
Label
Label
Label
Label
Label
Label
SDI
SDI
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
ARINC bit 32
31 - 11
10
9
8
7
6
5
4
3
2
1
CR11=1
Data
Label (MSB)
Label (LSB)
The HI-3585 accepts signals within these tolerances and rejects
signals outside these tolerances. Receiver logic achieves this as
described below:
1. An accurate 1MHz clock source is required to validate the
receive signal timing. Less than 1% error is recommended.
2. The receiver uses three separate 10-bit sampling shift reg-
isters for Ones detection, Zeros detection and Null detection.
When the input signal is within the differential voltage range
for any shift register’s state (One Zero or Null) sampling
clocks a high bit into that register. When the receive signal is
outside the differential voltage range defined for any shift reg-
ister, a low bit is clocked. Only one shift register can clock a
high bit for any given sample. All three registers clock low
bits if the differential input voltage is between defined state
voltage bands.
Valid data bits require at least three consecutive One or Zero
samples (three high bits) in the upper half of the Ones or
Zeros sampling shift register, and at least three consecutive
Null samples (three high bits) in the lower half of the Null sam-
pling shift register within the data bit interval.
A word gap Null requires at least three consecutive Null sam-
ples (three high bits) in the upper half of the Null sampling
shift register and at least three consecutive Null samples
(three high bits) in the lower half of the Null sampling shift reg-
ister. This guarantees the minimum pulse width.
Label
Label
Label
Label
Label
Parity
ARINC 429 RECEIVER
ARINC BUS INTERFACE
Figure 1 shows the input circuit for the on-chip ARINC 429 line
receiver. The ARINC 429 specification requires the following
detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
RINA-40
VDD
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
RINA
GND
VDD
Label
SDI
SDI
ONE
NULL
ZERO
RINB
RINB-40
GND
3. To validate the receive data bit rate, each bit must follow
its preceding bit by not less than 8 samples and not more
than 12 samples. With exactly 1MHz input clock frequency,
the acceptable data bit rates are:
HIGH SPEED
DATA BIT RATE MIN
DATA BIT RATE MAX
83K BPS
125K BPS
LOW SPEED
10.4K BPS
15.6K BPS
FIGURE 1. ARINC RECEIVER INPUT
The HI-3585 guarantees recognition of these levels with a common
mode voltage with respect to GND less than ±30V for the worst case
condition (3.15V supply and 13V signal level).
Design tolerances guarantee detection of the above levels, so the
actual acceptance ranges are slightly larger. If the ARINC signal
(including nulls) is outside the differential voltage ranges, the HI-
3585 receiver rejects the data.
4. Following the last data bit of a valid reception, the Word
Gap timer samples the Null shift register every 10 input
clocks (every 80 clocks for low speed). If a Null is present,
the Word Gap counter is incremented. A Word Gap count of
3 enables the next reception.
HOLT INTEGRATED CIRCUITS
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