®
ISD2500 Series
Single-Chip Voice Record/Playback Devices
32-*, 40-*, 48-*, 64-*
, 60-, 75-,
90-, and 120-Second Durations
FEATURES
•
•
•
Easy-to-use single-chip voice Record/
Playback solution
High-quality, natural voice/audio
reproduction
Manual switch or microcontroller compati-
ble Playback can be edge- or level-
activated
Single-chip durations of
32*, 40*, 48*, 64*
,
60, 75, 90, and 120 seconds
Directly cascadable for longer durations
Automatic Power-Down (Push-Button
Mode)
– Standby current 1
µA
(typical)
Zero-power message storage
– Eliminates battery backup circuits
•
•
•
•
•
•
•
•
Fully addressable to handle multiple
messages
100-year message retention (typical)
100,000 record cycles (typical)
On-chip clock source
No algorithm development required
Single +5 volt power supply
Available in die form, DIP, SOIC, and
TSOP packaging
Industrial temperature (-40°C to +85°C)
versions available
1
•
•
•
•
ISD2500 SERIES SUMMARY
Part
Number
ISD2560
ISD2575
ISD2590
ISD25120
Duration
(Seconds)
60
75
90
120
Input Sample
Rate (KHz)
8.0
6.4
5.3
4.0
Typical Filter
Pass Band (KHz)
3.4
2.7
2.3
1.7
ISD2532*
ISD2540*
ISD2548*
ISD2564*
32
40
48
64
8.0
6.4
5.3
4.0
3.4
2.7
2.3
1.7
Information Storage Devices, Inc.
*
Advance information: ISD2532/40/48/64 devices.
1–79
ISD2500 Series
Product Data Sheets
GENERAL DESCRIPTION
Information Storage Devices' ISD2500 Chip-
Corder
®
Series provides high-quality, single-chip
Record/Playback solutions for 32- to 120-second
messaging applications. The CMOS devices
include an on-chip oscillator, microphone pream-
plifier, automatic gain control, antialiasing filter,
smoothing filter, speaker amplifier, and high den-
sity multi-level storage array. In addition, the
ISD2500 is microcontroller compatible, allowing
complex messaging and addressing to be
achieved.
Recordings are stored in on-chip nonvolatile mem-
ory cells, providing zero-power message storage.
This unique, single-chip solution is made possible
through ISD's patented multilevel storage technol-
ogy. Voice and audio signals are stored directly
into memory in their natural form, providing high-
quality, solid-state voice reproduction.
DETAILED DESCRIPTION
Speech/Sound Quality
The ISD2500 Series includes devices offered at
4.0, 5.3, 6.4, and 8.0 KHz sampling frequencies,
allowing the user a choice of speech quality
options. Increasing the duration within a product
series decreases the sampling frequency and
bandwidth, which affects sound quality. Please
refer to the ISD2500 Series Summary table on
page 1-79 to compare filter pass band and product
durations.
The speech samples are stored directly into on-
chip nonvolatile memory without the digitization
and compression associated with other solutions.
Direct analog storage provides a very true, natural
sounding reproduction of voice, music, tones, and
sound effects not available with most solid-state
digital solutions.
-1
Duration
To meet end system requirements, the ISD2500
Series offers single-chip solutions at
32*, 40*, 48*,
64
*, 60, 75, 90, and 120 seconds. Parts may also
be cascaded together for longer durations.
ISD2560/75/90/120 DEVICE BLOCK DIAGRAM
Internal Clock
XCLK
5-Pole Active
Antialiasing Filter
Timing
Sampling Clock
R
ANA IN
ANA OUT
MIC
MIC REF
AGC
Pre-
Amp
Amp
Analog Transceivers
Decoders
480 K Cell
Nonvolatile
Multilevel Storage
Array
5-Pole Active
Smoothing Filter
SP+
Mux
Amp
SP–
Automatic
Gain Control
(AGC)
Power Conditioning
Address Buffers
Device Control
V
CCA
V
SSA
V
SSD
V
CCD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
PD OVF P/R
CE EOM AUX IN
1–80
*
Advance information: ISD2532/40/48/64 devices.
Product Data Sheets
ISD2500 Series
ISD2532/40/48/64
* DEVICE BLOCK DIAGRAM
Internal Clock
XCLK
5-Pole Active
Antialiasing Filter
Decoders
Timing
Sampling Clock
Amp
Analog Transceivers
256 K Cell
Nonvolatile
Multilevel Storage
Array
R
ANA IN
ANA OUT
MIC
MIC REF
AGC
Pre-
Amp
5-Pole Active
Smoothing Filter
SP+
Mux
Amp
SP–
Automatic
Gain Control
(AGC)
Power Conditioning
Address Buffers
Device Control
V
CCA
V
SSA
V
SSD
V
CCD
A0 A1 A2 A3 A4 A5
A6 A7
A8
PD OVF P/R
CE EOM AUX IN
EEPROM Storage
One of the benefits of ISD’s ChipCorder technol-
ogy is the use of on-chip nonvolatile memory,
providing zero-power message storage. The mes-
sage is retained for up to 100 years typically
without power. In addition, the device can be re-
recorded typically over 100,000 times.
PIN DESCRIPTIONS
Voltage Inputs (V
CCA
, V
CCD
)
To minimize noise, the analog and digital circuits in
the ISD2500 Series devices use separate power
busses. These voltage busses are brought out to
separate pins and should be tied together as close
to the supply as possible. In addition, these sup-
plies should be decoupled as close to the package
as possible.
1
Microcontroller Interface
In addition to its simplicity and ease of use, the
ISD2500 Series includes all the interfaces neces-
sary for microcontroller-driven applications. The
address and control lines can be interfaced to a
microcontroller and manipulated to perform a vari-
ety of tasks, including message assembly,
message concatenation, predefined fixed mes-
sage segmentation, and message management.
Ground Inputs (V
SSA
, V
SSD
)
The ISD2500 Series of devices utilizes separate
analog and digital ground busses. These pins
should be connected separately through a low-
impedance path to power supply ground.
Power Down Input (PD)
Programming
The ISD2500 Series is also ideal for playback-only
applications, where single or multiple messages
are referenced through buttons, switches, or a
microcontroller. Once the desired message config-
uration is created, duplicates can easily be
generated via an ISD programmer.
When not recording or playing back, the PD pin
should be pulled HIGH to place the part in a very
low power mode (see I
SB
specification). When
OVF pulses LOW for an overflow condition, PD
should be brought HIGH to reset the address
pointer back to the beginning of the Record/Play-
back space. The PD pin has additional
functionality in the M6 (Push-Button) Operational
*
Advance information: ISD2532/40/48/64 devices.
1–81
ISD2500 Series
Product Data Sheets
ISD2560/75/90/120 DEVICE PINOUTS
OVF
CE
PD
EOM
XCLK
P/R
V
CCD
NC
NC
A0/M0
A1/M1
A2/M2
A3/M3
A4/M4
A5/M5
A6/M6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ISD2560/75/90/120
ANA OUT
ANA IN
AGC
MIC REF
MIC
V
CCA
SP–
NC
NC
SP+
V
SSA
V
SSD
AUX IN
A9
A8
A7
A0/M0
A1/M1
A2/M2
A3/M3
A4/M4
A5/M5
A6/M6
A7
A8
A9
AUX IN
V
SSD
V
SSA
SP+
1
2
3
4
5
6
7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ISD2560
ISD2575
8
ISD2590
9
ISD25120
10
11
12
13
14
V
CCD
P/R
XCLK
EOM
PD
CE
OVF
ANA OUT
ANA IN
AGC
MIC REF
MIC
V
CCA
SP–
TSOP
DIP/SOIC
Mode described later in the Operational Mode
section.
End-Of-Message / RUN Output (EOM)
A nonvolatile marker is automatically inserted at
the end of each recorded message. It remains
there until the message is recorded over. The
EOM output pulses LOW for a period of T
EOM
at
the end of each message.
In addition, the ISD2500 Series has an internal
V
CC
detect circuit to maintain message integrity
should V
CC
fall below 3.5V. In this case, EOM
goes LOW and the device is fixed in Playback-only
mode.
When the device is configured in Operational
Mode M6 (Push-Button Mode), this pin provides an
active-HIGH RUN signal, indicating the device is
currently recording or playing. This signal can con-
veniently drive an LED for a visual indicator of a
Record or Playback operation in process.
-1
Chip Enable Input (CE)
The CE pin is taken LOW to enable all Playback
and Record operations. The address inputs and
Playback/Record input (P/R) are latched by the
falling edge of CE. CE has additional functionality
in the M6 (Push-Button) Operational Mode
described later in the Operational Mode section.
Playback/Record Input (P/R)
The P/R input is latched by the falling edge of the
CE pin. A HIGH level selects a Playback cycle
while a LOW level selects a Record cycle. For a
Record cycle, the address inputs provide the start-
ing address and recording continues until PD or
CE is pulled HIGH or an overflow is detected (i.e.
the chip is full). When a Record cycle is terminated
by pulling PD or CE HIGH, an End-Of-Message
(EOM) marker is stored at the current address in
memory. For a Playback cycle, the address inputs
provide the starting address and the device will
play until an EOM marker is encountered. The
device can continue past an EOM marker in an
operational mode, or if CE is held LOW in address
mode. (See page 1-85 for more Operational
Modes).
Overflow Output (OVF)
This signal pulses LOW at the end of memory
space, indicating the device has been filled and the
message has overflowed. The OVF output then fol-
lows the CE input until a PD pulse has reset the
device. This pin can be used to cascade several
ISD2500 devices together to increase Record/
Playback durations.
1–82
*
Advance information: ISD2532/40/48/64 devices.
Product Data Sheets
ISD2500 Series
ISD2532/40/48/64
* DEVICE PINOUTS
OVF
CE
PD
EOM
XCLK
P/R
V
CCD
NC
NC
A0/M0
A1/M1
A2/M2
A3/M3
A4/M4
A5/M5
A6/M6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ISD2532/40/48/64
ANA OUT
ANA IN
AGC
MIC REF
MIC
V
CCA
SP–
NC
NC
SP+
V
SSA
V
SSD
AUX IN
A8
A7
NC
A0/M0
A1/M1
A2/M2
A3/M3
A4/M4
A5/M5
A6/M6
NC
A7
A8
AUX IN
V
SSD
V
SSA
SP+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ISD2532
ISD2540
ISD2548
ISD2564
V
CCD
P/R
XCLK
EOM
PD
CE
OVF
ANA OUT
ANA IN
AGC
MIC REF
MIC
V
CCA
SP–
TSOP
DIP/SOIC
Microphone Input (MIC)
The microphone input transfers its signal to the on-
chip preamplifier. An on-chip Automatic Gain Con-
trol (AGC) circuit controls the gain of this
preamplifier from -15 to 24 dB. An external micro-
phone should be AC coupled to this pin via a series
capacitor. The capacitor value, together with the
internal 10 K ohm resistance on this pin, deter-
mines the low-frequency cutoff for the ISD2500
Series passband. See ISD's
Application Notes and
Design Manual
in this book for additional informa-
tion on low-frequency cutoff calculation.
AGC pin to V
SSA
analog ground. The “release”
time is determined by the time constant of an
external resistor (R2) and an external capacitor
(C2) connected in parallel between the AGC Pin
and V
SSA
analog ground. Nominal values of
470 KΩ and 4.7
µF
give satisfactory results in
most cases.
1
Analog Output (ANA OUT)
This pin provides the preamplifier output to the
user. The voltage gain of the preamplifier is deter-
mined by the voltage level at the AGC pin.
Microphone Reference Input (MIC REF)
The MIC REF input is the inverting input to the
microphone preamplifier. This provides a noise-
canceling or common-mode rejection input to the
device when connected to a differential
microphone.
Analog Input (ANA IN)
The analog input pin transfers its signal to the chip
for recording. For microphone inputs, the ANA
OUT pin should be connected via an external
capacitor to the ANA IN pin. This capacitor value,
together with the 3.0 KΩ input impedance of ANA
IN, is selected to give additional cutoff at the low-
frequency end of the voice passband. If the
desired input is derived from a source other than a
microphone, the signal can be fed, capacitively
coupled, into the ANA IN pin directly.
Automatic Gain Control Input (AGC)
The AGC dynamically adjusts the gain of the
preamplifier to compensate for the wide range of
microphone input levels. The AGC allows the full
range of whispers to loud sounds to be recorded
with minimal distortion. The “attack” time is deter-
mined by the time constant of a 5 KΩ internal
resistance and an external capacitor (C2 on the
schematic on page 1-100) connected from the
External Clock Input (XCLK)
The external clock input for the ISD2500 devices
has an internal pull-down device. These devices
are configured at the factory with an internal sam-
pling clock frequency centered to
±1%
of
*
Advance information: ISD2532/40/48/64 devices.
1–83
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