Dual DVB-T/C/S/S2 Digital TV Demodulator
Description
The Si21672-B integrates two separate high-performance
DVB-T, DVB-C, DVB-S, and DVB-S2 digital demodulators into
a single compact package for terrestrial, cable, and satellite
TV standards. Leveraging Silicon Labs' proven digital
demodulation architecture, each embedded demodulator
achieves excellent reception performance for each media
while significantly minimizing front-end design complexity and
cost. Connecting the Si21672-B to both a dual terrestrial/
cable TV tuner, and a dual satellite tuner, results in a
high-performance and cost optimized TV front-end solution.
The DVB-T and DVB-C demodulators are enhanced versions
of proven and broadly used Si2167/68/69 Silicon Labs
devices. Furthermore, ITU J.83 Annex B is also supported for
US and South American cable networks. The IF input
supports standard IF (36 MHz) or low-IF.
The satellite demodulation functionality allows demodulating
widely deployed DVB-S, DIRECTV™ (DSS) legacy
standards, and DVB-S2 (AMC compliant)) satellite
broadcasts. A zero-IF interface allows for a seamless
connection to market proven satellite silicon tuners.
The Si21672-B offers an on-chip blind scanning algorithm for
DVB-S/S2 and DVB-C standards (as well as blind lock). It
also integrates two DiSEqC™ 2.0 LNB interfaces for satellite
dish control and, for each satellite demodulator, an equalizer
to compensate for echoes in long cable feeds from the LNB to
the satellite tuner RF input.
The Si21672-B embeds two independent programmable
transport stream interfaces which provide a flexible range of
output modes and are fully compatible with all MPEG
decoders or conditional access modules to support any
customer application.
Si21672-B22
Features
-
DVB-T (ETSI EN 300 744)
-
COFDM demodulator and enhanced FEC decoder
-
NorDig Test Spec 2.2.2, D-Book 7 V3 compliant
-
DVB-C (ETSI EN 300 429) / ITU J.83 Annex A/B/C
-
QAM demodulator and FEC decoder
-
1 to 7.2 MSymbol/s
-
C-Book compliant
-
DVB-S2 (ETSI EN 302 307 and TR102-376)
-
QPSK/8PSK demodulator and FEC decoder
-
Broadcast profile: CCM, 64800 bits frame, single TS
-
1 to 45 MSymbol/s
-
DIRECTV™ AMC compatible
-
DVB-S (ETSI EN 300 421) and DSS supported
-
QPSK demodulator and enhanced FEC decoder
-
1 to 45 MSymbol/s
-
Dual DiSEqC™ 2.x interface, Unicable support
-
I
2
C serial bus interfaces (master and host)
-
Dual independent differential IF input for T/C tuners and
-
GPIOs and multi-purpose ports (two per demodulator)
-
Firmware control for upgradeability
-
Separate flexible TS interfaces with serial or parallel
-
-
-
-
differential ZIF I/Q inputs for satellite tuners
outputs
Fast lock times for all standards
Only two power supplies: 1.2 and 3.3 V
8x8 mm, QFN-68 pin package, Pb-free/RoHS compliant
Pin-to-pin compatible with all dual demodulator family:
Si216x2
-
API compatible with all single and dual demodulator
families
Applications
-
-
-
-
Multi-receiver iDTV: on-board or in a NIM
Advanced multimedia PVR STBs
PC-TV accessories
PVR, DVD, and Blu-Ray disc recorders
1.2, 3.3V
RESETB
MP_A_A
MP_C_A
S_ADC_IP_A
S_ADC_IN_A
S_ADC_QP_A
S_ADC_QN_A
TC_ADC_P_A
TC_ADC_N_A
DiSEqC_OUT_A
DiSEqC_CMD
DiSEqC_IN_A_B
SDA_MAST
SCL_MAST
XO
XTAL_I/CLK_IN
CLK_IN/OUT
Si21672B
ADC_A
ADC_A
ADC_A
DiSEqC_A
I2C Block_A
GPIO1/TS_ERR_A
TS_VAL_A
TS_SYNC_A
TS_CLK_A
TS_DATA_A
ADDR_A
Dual Satellite
Tuner
DEMODULATOR_A CORE
8
SDA_HOST
SCL_HOST
TV Tuner
DiSEqC_OUT_B
DiSEqC_B
ADC_B
ADC_B
ADC_B
I2C Block_B
ADDR_B
GPIO0/TS_ERR_B
TV Tuner
TC_ADC_P_B
TC_ADC_N_B
S_ADC_IP_B
S_ADC_IN_B
S_ADC_QP_B
S_ADC_QN_B
MP_B_B
MP_D_B
DEMODULATOR_B CORE
TS_VAL_B
TS_SYNC_B
TS_CLK_B
TS_DATA_B
8
Dual Digital Demodulators
Copyright © 2015 by Silicon Laboratories
HDTV MPEG S.o.C.
10.29.2015
Dual DVB-T/C/S/S2 Digital TV Demodulator
Selected Electrical Specifications
(T
A
= –10 to 70 °C)
.
Parameter
General
Input clock reference
Supported XTAL frequency
Total power consumption for
each demodulator
Thermal resistance (
JA
)
Power Supplies
V
DD
_
VCORE
V
DD
_
VANA
V
DD
_
VIO
Si21672-B22
Test Condition
Min
4
16
—
—
—
1.14
3.00
3.00
Typ
—
—
172/161
240/465
42
1.20
3.30
3.30
Max
30
30
—
—
—
1.30
3.60
3.60
Unit
MHz
MHz
mW
mW
°C/W
V
V
V
DVB-T
1
/DVB-C
2
DVB-S
3
/DVB-S2
4
4 layer PCB
Notes:
1.
Test conditions: 8 MHz, 8K FFT, 64 QAM, parallel TS output.
2.
Test conditions: 6.9 MBaud, 256 QAM, parallel TS output.
3.
Test conditions: 30 MBaud, CR=7/8, parallel TS (at QEF: BER = 2. 10
–4
).
4.
Test conditions: 32 MBaud, 3/5 Code Rate, 8PSK, pilots On, parallel TS, C/N at picture failure.
Pin Assignments
GPIO_1/TS_ERR_A
XTAL_I/CLK_IN
TS_DATA[7]_A
TS_DATA[7]_B
TS_DATA[6]_B
TS_DATA[6]_A
TS_SYNC_A
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
S_ADC_IN_A
52
TS_DATA[5]_B
S_ADC_IP_A
VDD_CORE
VDD_CORE
VDD_ANA
ADDR_A
ADDR_B
RESETB
MP_C_A
MP_D_B
XO
34
TS_DATA[5]_A
S_ADC_QP_A
53
S_ADC_QN_A
54
33
VDD_VIO
32
GND
31
VDD_CORE
S_ADC_IP_B
55
S_ADC_IN_B
56
S_ADC_QP_B
57
30
VDD_CORE
S_ADC_QN_B
58
TC_ADC_P_A
59
TC_ADC_N_A
60
Si21672B
(GND_PAD)
29
TS_DATA[4]_B
28
TS_DATA[4]_A
27
TS_DATA[3]_B
26
TS_DATA[3]_A
TC_ADC_P_B
61
TC_ADC_N_B
62
CLK_IN_OUT
63
SDA_MAST
64
SCL_MAST
65
GND
66
QFN-68
8x8mm
25
TS_DATA[2]_B
24
TS_DATA[2]_A
23
TS_DATA[1]_B
22
TS_DATA[1]_A
21
TS_DATA[0]_B/TS_SER_B
20
TS_DATA[0]_A/TS_SER_A
19
TS_CLK_B
18
TS_CLK_A
VDD_CORE
67
VDD_CORE
68
1
MP_A_A
2
MP_B_B
3
GPIO_0/TS_ERR_B
4
DISEQC_CMD_A
5
DISEQC_IN_A_B
6
DISEQC_OUT_A
7
DISEQC_OUT_B
8
VDD_CORE
9 10 11 12
13 14 15 16 17
GND
TS_VAL_A
Selection Guide
Part #
Si21672-B22-GM/R
Dual Digital Demodulators
Description
Dual Digital TV Demodulator for DVB-T/C/S/S2, 8x8 mm QFN-68
Copyright © 2015 by Silicon Laboratories
10.29.2015
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
TS_SYNC_B
VDD_CORE
SCL_HOST
SDA_HOST
TS_VAL_B
VDD_VIO
嵌入式系统
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