LVITD
Series
LVC Low Voltage Logic
10-Tap Delay Modules
Inputs accept voltages up to 5.5 V
74LVC type input can be driven from either 3.3V or 5V
devices. This allows delay module to serve as a
translator in a mixed 3.3V / 5V system environment.
Operating Temp. -40
O
C to +85
O
C
Low Profile 14-Pin Package
Two Surface Mount Versions
For 5-Tap 8-Pin Versions see LVMDM Series
Electrical Specifications at 25
O
C
LVC Logic
10 Tap P/N
LVITD-12
LVITD-21
LVITD-30
LVITD-50
LVITD-60
LVITD-75
LVITD-80
LVITD-100
LVITD-125
LVITD-150
Tap Delay Tolerances +/- 5% or 2ns (>15ns +/- 1.0ns)
Tap 1
Tap 2
Tap 3
Tap 4
Tap 5
Tap 6
Tap 7
Tap 8
Tap 9
Total - Tap 10
LVITD Schematic
Vcc
14
Tap1 Tap3 Tap5 Tap7 Tap9 Tap10
13
12
11
10
9
8
1
IN
2
N/C
3
4
5
6
7
Tap2 Tap4 Tap6 Tap8 GND
Tap-to-Tap
(ns)
1.0 ± 0.4
2.0 ± 0.6
3.0 ± 0.8
5.0 ± 1.8
6.0 ± 2.0
7.5 ± 2.0
8.0 ± 2.0
10.0 ± 2.0
12.5 ± 3.0
15.0 ± 3.0
3
3
3
5
6
7.5
8
10
12.5
15
4
5
6
10
12
15
16
20
25
30
5
7
9
15
18
22.5
24
30
37.5
45
6
9
12
20
24
30
32
40
50
60
7
11
15
25
30
37.5
40
50
62.5
75
8
13
18
30
36
45
48
60
75
90
9
15
21
35
42
52.5
56
70
87.5
105
10
17
24
40
48
60
64
80
100
120
11
19
27
45
54
67.5
72
90
112.5
135
12 ± 2.5
21 ± 2.5
30 ± 2.5
50 ± 2.5
60 ± 3.0
75 ± 3.75
80 ± 4.0
100 ± 5.0
125 ± 6.25
150 ± 7.5
TEST CONDITIONS
-- Low Voltage CMOS, LVC
V
CC
Supply Voltage ................................................ 3.30VDC
Input Pulse Voltage ................................................... 2.70V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25
O
C
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 50pf probe and fixture load on output under test.
.785
(19.94)
MAX.
Dimensions in Inches (mm)
.285
(7.24)
MAX.
.250
.020 (6.35)
(0.51) MAX.
.120
(3.05)
MIN.
.050
(1.27)
TYP.
DIP
DIP
.008 R
(0.20)
.010
(0.25)
TYP.
.300
(7.62)
.365
(9.27)
MAX.
OPERATING SPECIFICATIONS
Supply Voltage, V
CC
.......................................... 3.3
±
0.3 VDC
Supply Current, I
CC
........................... 10 mA typ., 30 mA max.
Supply Current, I
CCL
: V
IN
= GND ......................... 22 mA max.
Supply Current, I
CCH
: V
IN
= V
CC
............................. 10
µA
max.
Input Voltage, V
I
..................................... 0 V min., 5.5 V max.
Logic “1” Input, V
IH
.................................................. 2.0 V min.
Logic “0” Input, V
IL
................................................. 0.8 V max.
Logic “1” Out, V
OH
: V
CC
= 3V & I
OH
= -24 mA ............ 2.0 V min.
Logic “0” Out, V
OL
: V
CC
= 3V & I
OL
= 24 mA ......... 0.55 V max.
Input Capacitance, C
I
............................................. 5 pF, typ.
Input Pulse Width, P
WI
.............................. 40% of Delay min.
Operating Temperature Range ......................... -40
O
to +85
O
C
Storage Temperature Range ........................ -65
O
to +150
O
C
.020
(0.51)
TYP.
.100
(2.54)
TYP.
.785
(19.94)
MAX.
.285
(7.24)
MAX.
.250
(6.35)
MAX.
.015
(0.38)
TYP.
.030
(0.76)
TYP.
G-SMD
G-SMD
.008 R
(0.20)
.010
(0.25)
TYP.
.020
(0.51)
TYP.
.050
(1.27)
TYP.
.785
(19.94)
MAX.
.100
(2.54)
TYP.
.430 (10.92)
.400 (10.16)
.285
(7.24)
MAX.
P/N Description
LVITD
-
XXX X
LVC Buffered 10 Tap Delay
Molded Package Series:
14-pin DIP:
LVITD
Total Delay in nanoseconds (ns)
Lead Style: Blank = Thru-hole
G = “Gull Wing” SMD
J = “J” Bend SMD
Examples: LVITD-30G =
LVITD-100 =
J-SMD
.265
(6.73)
MAX.
.030
(0.76)
TYP.
J-SMD
.285 (7.24)
.260 (6.60)
.330 (8.38)
MAX.
.020 R
(0.51)
.020
(0.51)
TYP.
.050
(1.27)
TYP.
.100
(2.54)
TYP.
30ns (3ns per tap) 74LVC, 14-Pin G-SMD
100ns (10ns per tap) 74LVC, 14-Pin DIP
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19
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