SPECIFICATION
for
MRD520A
Dual Channel F2F Decoder IC
Uniform Industrial Corp.
Taiwan, Factory
1st FL., No.1, Lane 15,
Chih Chiang Street,
Tu Cheng City, Taipei Hsien,
Taiwan, R.O.C.
Tel
Fax
E-mail
: 886-2-268-7075
: 886-2-268-6327
: uniform@ms1.hinet.com
USA, Office
46750 Fremont Blvd
Suite 104
Fremont, CA 94538
USA
Tel
Fax
E-mail
: 1-510-438-6799
: 1-510-438-6790
: uicu@aol.com
PREPARED BY
APPROVED BY
CHECK BY
CONTENTS
1. DESCRIPTION..................................................................................................... 1
2. FEATURES.......................................................................................................... 1
3. APPLICATIONS .................................................................................................. 1
4. PIN DESCRIPTION ............................................................................................. 2
5. FUNCTION DESCRIPTION................................................................................ 3
6. ABSOLUTE MAXIMUM RATINGS ................................................................... 4
7. RECOMMENDED OPERATING CONDITIONS............................................... 4
8. APPLICATION CIRCUIT .................................................................................... 5
9. TIMING DIAGRAM FOR MRD520A.................................................................. 6
10. OUTLINE DIMENSION ..................................................................................... 7
Uniform Industrial Corp.
MRD520A
Dual Channel F2F Decoder IC
1. DESCRIPTION
The MRD520A is a 1.2um CMOS integrated circuit for purpose of amplification and
decoding for F2F magnetic stripe encoding card reader.
2. FEATURES
l
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Integrated Amplification Circuitry for magnetic head signals.
Number of start bits (4/8 bits) to ignore selectable.
Both output polarity supported.
Adjustable read data output clock pulse width.
Dual channel support for 75/210 BPI recording density.
Magnetic head data input frequency range from 300 bit/sec to 12600 bit/sec.
Idle mode controllable by external hardware or micro-processor.
3. APPLICATIONS
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Magnetic stripe card reader.
POS keyboard.
PIN Configuration (Top View)
GND
SEN1N
SEN1P
OP1OUT
OP2NIN
OP2OUT
OP3OUT
OP6OUT
OP5OUT
OP5NIN
OP4OUT
SEN2P
SEN2N
VREFIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RES
ADJ1
CLS
OUT1
OUT1X
OCK1
IBS
OSCO
OSCI
OCK2
OUT2X
OUT2
ADJ2
VDD
OUTLINE SOP 28 PIN
Page : 1
October, 1997
Uniform Industrial Corp.
MRD520A
Dual Channel F2F Decoder IC
4. PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
SEN1N
SEN1P
OP1OUT
OP2NIN
OP2OUT
OP3OUT
OP6OUT
OP5OUT
OP5NIN
OP4OUT
SEN2P
SEN2N
VREFIN
VDD
ADJ2
OUT2
OUT2X
OCK2
OSCI
OSCO
IBS
OCK1
OUT1X
OUT1
CLS
ADJ1
RES
Adjust read out clock pulse width for F2F channel 2
Positive read out data for F2F channel 2
Negative read out data for F2F channel 2
Negative read out clock for F2F channel 2
RC oscillator input
RC oscillator output
Select ignore leading bit, “LOW” for 4 bits and “HIGH” for 8 bits
Negative read out clock for F2F channel 1
Negative read out data for F2F channel 1
Positive read out data for F2F channel 1
Card Loading Signal output, “LOW” after ignore bits,
“HIGH” if no input for around 12.5mS
Adjust read out clock pulse width for F2F channel 1
Power on reset, LOW reset the logic circuit and enter idle mode.
Approx. 10mS after HIGH level to normal function
Input from magnetic head
Input from magnetic head
Amplifier OP1 output
Amplifier OP2 - input
Amplifier OP2 output
Amplifier OP3 output
Amplifier OP6 output
Amplifier OP5 output
Amplifier OP5 - input
Amplifier OP4 output
Amplifier OP4 + input
Amplifier OP4 - input
Reference voltage for analog signal processing
Page : 2
October, 1997
Uniform Industrial Corp.
MRD520A
Dual Channel F2F Decoder IC
5. FUNCTION DESCRIPTION
Data signal inputs read from a magnetic card via a magnetic head are fed into the SEN1P
and SEN1N (SEN2P and SEN2N) pins, amplified and wave shaped by internal analog
circuitry, then converted to logic level F2F data format. Once the F2F signals are detected,
the decoding logic ignores the leading 4 or 8 bits (set by IBS pin), via the ignored bits the
reference bit length is determined. The succeeding inputs are identified as bit 0 or 1 by
the average bit length of preceding two bits, if the data toggles before 70% of the
reference bit length then the data is identified as a “1” bit and the next data toggle regarded
as the beginning of next data bit. If the data toggles after 70% of the reference bit length
then the data is identified as a “0” bit and the current data toggle is as the beginning of next
data.
After the ignored bits, then pin CLS will be pulled low, the succeeding data bit will be shifted
out after the beginning of next data bit.
The pin OCK1 (OCK2) will be pulled low after the next data is detected and a 12uS delay
inserted, it will be kept low for 14 to 60uS depending on the external resistor connected to
pin ADJ1 (ADJ2). If the next bit comes before OCK1 (OCK2) goes high, then OCK1
(OCK2) will be forced to pull high and then begins next cycle, it means that the data signals
will be ready before OCK1 (OCK2) goes low and stay valid till 12uS before next down edge
of OCK1 (OCK2).
Page : 3
October, 1997
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