PRODUCT SPECIFICATION
433MHz Single Chip RF Transmitter
FEATURES
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•
•
•
•
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True single chip FSK transmitter
Few external components required
On chip UHF synthesiser
No set up or configuration
20kbit/s data rate
2 channels
Very low power consumption
Standby mode
nRF402
APPLICATIONS
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•
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Alarm Systems
Automatic Meter Reading (AMR)
Keyless entry
Home Automation
Remote Control
Surveillance
Automotive
Telemetry
Toys
Wireless Communication
GENERAL DESCRIPTION
nRF402 is a true single chip UHF transmitter designed to operate in the 433MHz ISM
(Industrial, Scientific and Medical) frequency band. It features Frequency Shift
Keying (FSK) modulation capability. nRF402 operates at data rates up to 20kbits/s.
Transmit power can be adjusted to a maximum of +10dBm. Antenna interface is
differential and suited for low cost PCB antennas. nRF402 operates from a single 3V
DC supply and has a standby mode which makes power saving easy and efficient.
As a primary application, nRF402 is intended for UHF radio equipment in compliance
with the European Telecommunication Standard Institute (ETSI) specification
EN 300 220-1 V1.2.1.
QUICK REFERENCE DATA
Parameter
Frequency, Channel#1/Channel#2
Modulation
Frequency deviation
Max. RF output power @ 400Ω, 3V
Maximum bit rate
Supply voltage
Transmit supply current @ -10 dBm RF output power
Standby supply current
Value
433.92 / 434.33
FSK
±15
10
20
2.7 – 3.6
8
8
Unit
MHz
kHz
dBm
kbit/s
V
mA
µA
Table 1. nRF402 quick reference data
ORDERING INFORMATION
Type number
nRF402-IC
nRF402-EVKIT
Description
14 pin SSOIC
Evaluation kit with nRF402 IC
Version
A
1.0
Table 2. nRF402 ordering information
Nordic VLSI ASA
Revision: 2.1
-
Vestre Rosten 81, N-7075 Tiller, Norway
Page 1 of 16
-
Phone +4772898900
-
Fax +4772898989
February 2000
PRODUCT SPECIFICATION
nRF402 Single Chip RF Transmitter
BLOCK DIAGRAM
CS
7
DIN
9
11
PWR_UP
13
OSC
PLL
LOOP
FILTER
4
VCO
PA
10
ANT1
ANT2
1
14
6
5
8
LPF
VCO
INDUCTOR
RF_PWR
REFERENCE
Figure 1. nRF402 block diagram with external components
PIN FUNCTIONS
Pin
1
2
3
4
5
6
7
Name
XC1
VSS
VDD
VCO1
VCO2
LPF
CS
Pin function
Input
Ground
Power
Input
Input
Test
Input
Description
Crystal oscillator input
Ground (0V)
Power supply (+3V DC)
External inductor for VCO
External inductor for VCO
Loop filter voltage test pin *
Channel selection
CS=“0”
⇒
433.92MHz, (Channel#1)
CS=“1”
⇒
434.33MHz, (Channel#2)
Transmit power setting
Data input
Antenna terminal
Antenna terminal
Ground (0V)
Power on/off
PWR_UP = “1”
⇒
Power up (Transmit mode)
PWR_UP = “0”
⇒
Power down (Standby mode)
Crystal oscillator output
8
9
10
11
12
13
RF_PWR
DIN
ANT2
ANT1
VSS
PWR_UP
Input
Input
Output
Output
Ground
Input
14
XC2
Output
Table 3. nRF402 pin functions
*)
This pin is only for test purposes and is intended for use when measuring the loop filter voltage.
Nordic VLSI ASA
Revision: 2.1
Vestre Rosten 81, N-7075 Tiller, Norway
-
Page 2 of 16
Phone +4772898900
-
Fax +4772898989
February 2000
PRODUCT SPECIFICATION
nRF402 Single Chip RF Transmitter
ELECTRICAL SPECIFICATIONS
Conditions: VDD = +3V DC, VSS = 0V, T
A
= -25°C to +85°C
Symbol
VDD
VSS
I
DD
Parameter (condition)
Supply voltage
Ground
Current consumption in transmit mode
@ -10 dBm RF power
Current consumption in standby mode
Max. RF output power @ 400Ω load
Logic “1” input voltage
Logic “0” input voltage
Logic “1” input current (V
I
= VDD)
Logic “0” input current (V
I
= VSS)
Channel#1 frequency
Channel#2 frequency
Modulation type
Frequency deviation
Crystal frequency
1)
Bit rate
Recommend antenna port differential load
impedance
Spurious emission
Min.
2.7
Typ.
3
0
8
8
10
Max.
3.6
Units
V
V
mA
µA
dBm
V
V
µA
µA
MHz
MHz
kHz
MHz
kbit/s
Ω
I
DD
P
RF
V
IH
V
IL
I
H
I
L
f
1
f
2
∆f
f
XTAL
Z
I
0.7⋅V
DD
0
V
DD
0.3⋅V
DD
+20
-20
433.92
434.33
FSK
±15
4.000
0
400
20
Compliant with EN 300-220-1 V1.2.1
2)
Table 4. nRF402 electrical specifications
1) Crystal stability requirement must match the receiver requirement. For use with nRF401, the
crystal frequency stability should be better than ±45 ppm.
2) With PCB loop antenna or differential to single ended matching network to a 50Ω antenna.
ABSOLUTE MAXIMUM RATINGS
Supply voltages
VDD .............................. - 0.3V to +6V
VSS ................................................ 0V
Input voltage
V
I
...................... - 0.3V to VDD + 0.3V
Total power dissipation
P
D
(T
A
=85°C).......................... 230 mW
Temperatures
Operating Temperature -25°C to +85°C
Storage Temperature - 40°C to +125°C
Note: Stress exceeding one or more of the limiting values may cause permanent
damage to the device.
ATTENTION!
Electrostatic Sensitive Device
Observe Precaution for handling.
Nordic VLSI ASA
Revision: 2.1
Vestre Rosten 81, N-7075 Tiller, Norway
-
Page 3 of 16
Phone +4772898900
-
Fax +4772898989
February 2000
PRODUCT SPECIFICATION
nRF402 Single Chip RF Transmitter
PIN ASSIGNMENT
XC1
VSS
VDD
VCO1
VCO2
LPF
CS
1
2
3
4
5
6
7
14
XC2
nRF402
14 pin SSOIC
13
PWR_UP
12
VSS
11
ANT1
10
ANT2
9
8
DIN
RF_PWR
Figure 2. nRF402 pin assignment
PACKAGE OUTLINE
nRF402, 14 pin SSOIC. Dimensions in mm
14 13 12
E
H
1 2 3
D
A
1
A
L
e
b
α
Package Type
14 pin SSOIC
(5.3 mm)
Min
Max
D
5.90
6.50
E
5.00
5.60
H
7.40
8.20
A
2.00
A
1
0.05
e
0.65
b
0.22
0.38
L
0.55
0.95
Copl.
0.10
α
0°
8°
Figure 3. SSOIC-14 Package outline
Nordic VLSI ASA
Revision: 2.1
Vestre Rosten 81, N-7075 Tiller, Norway
-
Page 4 of 16
Phone +4772898900
-
Fax +4772898989
February 2000
PRODUCT SPECIFICATION
nRF402 Single Chip RF Transmitter
IMPORTANT TIMING DATA
Timing information
The timing information for the different operations is summarised in Table 5.
(TX is transmit mode, Std.by is standby mode.)
Change of Mode
Std.byè TX
V
DD
=0
è
TX
Name
t
ST
t
VT
Max Delay
2ms
4ms
Condition
Operational
mode
Start-up
Table 5 Switching times for nRF402
Switching between standby and TX-mode.
The maximum time from the PWR_UP input is set to “1”, until the synthesised
frequency is stable is t
ST
, see Table 5 and Figure 4.
Std.by to TX
VDD
PWR_UP
DIN
2ms
ms
0
2
4
Figure 4 Timing diagram for nRF402 when going from standby to TX-mode
Powering up to transmit-mode (start-up).
Due to spurious emission when the power supply is switched on, the PWR_UP-input
must be kept low for 2ms after VDD > 2.7 V. Data (DIN) is valid within 2ms after
PWR_UP is high.
VDD=0 to TX
VDD
PWR_UP
DIN
2ms
2ms
ms
0
2
4
Figure 5. Timing diagram for nRF402, when powering up to TX-mode
Nordic VLSI ASA
Revision: 2.1
Vestre Rosten 81, N-7075 Tiller, Norway
-
Page 5 of 16
Phone +4772898900
-
Fax +4772898989
February 2000
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