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HSP43168JC-45: 产品描述Digital Filter, 10-Bit, CMOS, PQCC84; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小429KB，共24页; 制造商Harris; 官网地址http://www.harris.com/

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HSP43168JC-45概述

Digital Filter, 10-Bit, CMOS, PQCC84

HSP43168JC-45规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	Harris
包装说明	QCCJ, LDCC84,1.2SQ
Reach Compliance Code	unknow
ECCN代码	3A001.A.3
其他特性	2 X 10 BIT DATA INPUT BUS; MULTIPLEXED OUTPUT; ICC SPECIFIED @ 33MHZ
边界扫描	NO
最大时钟频率	45.45 MHz
外部数据总线宽度	10
JESD-30 代码	S-PQCC-J84
JESD-609代码	e0
低功率模式	YES
端子数量	84
最高工作温度	70 °C
最低工作温度
输出数据总线宽度	28
封装主体材料	PLASTIC/EPOXY
封装代码	QCCJ
封装等效代码	LDCC84,1.2SQ
封装形状	SQUARE
封装形式	CHIP CARRIER
电源	5 V
认证状态	Not Qualified
最大压摆率	363 mA
最大供电电压	5.25 V
最小供电电压	4.75 V
标称供电电压	5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	J BEND
端子节距	1.27 mm
端子位置	QUAD
uPs/uCs/外围集成电路类型	DSP PERIPHERAL, DIGITAL FILTER
Base Number Matches	1

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S E M I C O N D U C T O R

HSP43168

Dual FIR Filter

Description

The HSP43168 Dual FIR Filter consists of two independent

8-tap FIR ﬁlters. Each ﬁlter supports decimation from 1 to 16

and provides on-board storage for 32 sets of coefﬁcients.

The Block Diagram shows two FIR cells each fed by a

separate coefﬁcient bank and one of two separate inputs.

The outputs of the FIR cells are either summed or

multiplexed by the MUX/Adder. The compute power in the

FIR Cells can be conﬁgured to provide quadrature ﬁltering,

complex ﬁltering, 2-D convolution, 1-D/2-D correlations, and

interpolating/decimating ﬁlters.

The FIR cells take advantage of symmetry in FIR

coefﬁcients by pre-adding data samples prior to

multiplication. This allows an 8-tap FIR to be implemented

using only 4 multipliers per ﬁlter cell. These cells can be

conﬁgured as either a single 16-tap FIR ﬁlter or dual 8-tap

FIR ﬁlters. Asymmetric ﬁltering is also supported.

Decimation of up to 16 is provided to boost the effective

number of ﬁlter taps from 2 to 16 times. Further, the

decimation registers provide the delay necessary for fractional

data conversion and 2-D ﬁltering with kernels to 16x16.

The ﬂexibility of the Dual is further enhanced by 32 sets of

user programmable coefﬁcients. Coefﬁcient selection may

be changed asynchronously from clock to clock. The ability

to toggle between coefﬁcient sets further simpliﬁes

applications such as polyphase or adaptive ﬁltering.

The HSP43168 is a low power fully static design

implemented in an advanced CMOS process. The

conﬁguration of the device is controlled through a standard

microprocessor interface.

December 1996

Features

• Two Independent 8-Tap FIR Filters Conﬁgurable as a

Single 16-Tap FIR

• 10-Bit Data and Coefﬁcients

• On-Board Storage for 32 Programmable Coefﬁcient Sets

• Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 19-Bit

Data and Coefﬁcients

• Programmable Decimation to 16

• Programmable Rounding on Output

• Standard Microprocessor Interface

Applications

• Quadrature, Complex Filtering

• Polyphase Filtering

• Image Processing

• Adaptive Filtering

Ordering Information

PART NUMBER

HSP43168VC-33

HSP43168VC-40

HSP43168VC-45

HSP43168JC-33

HSP43168JC-40

HSP43168JC-45

HSP43168JI-40

HSP43168GC-33

HSP43168GC-45

TEMP.

RANGE (

0 to 70

-40 to 85

0 to 70

PACKAGE

100 Ld MQFP

84 Ld PLCC

84 Ld CPGA

PKG. NO.

Q100.14x20

N84.1.15

G84.A

Block Diagram

CIN0 - 9

A0 - 8

CSEL0 - 4

CONTROL/

CONFIGURATION

COEFFICIENT

BANK A

INA0 - 9

FIR CELL A

MUX

COEFFICIENT

BANK B

FIR CELL B

INB0 - 9/

OUT0 - 8

MUX /

ADDER

OEL

OEH

OUT9 - 27

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Harris Corporation 1996

File Number

2808.6

HSP43168JC-45相似产品对比

	HSP43168JC-45	HSP43168JC-40	HSP43168JI-40	HSP43168VC-45	HSP43168VC-33	HSP43168VC-40
描述	Digital Filter, 10-Bit, CMOS, PQCC84	Digital Filter, 10-Bit, CMOS, PQCC84	Digital Filter, 10-Bit, CMOS, PQCC84	Digital Filter, 10-Bit, CMOS, PQFP100	Digital Filter, 10-Bit, CMOS, PQFP100	Digital Filter, 10-Bit, CMOS, PQFP100
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合
包装说明	QCCJ, LDCC84,1.2SQ	QCCJ, LDCC84,1.2SQ	QCCJ, LDCC84,1.2SQ	QFP, QFP100,.7X.9	QFP, QFP100,.7X.9	QFP, QFP100,.7X.9
Reach Compliance Code	unknow	unknow	unknow	unknown	unknown	unknown
边界扫描	NO	NO	NO	NO	NO	NO
外部数据总线宽度	10	10	10	10	10	10
JESD-30 代码	S-PQCC-J84	S-PQCC-J84	S-PQCC-J84	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
JESD-609代码	e0	e0	e0	e0	e0	e0
低功率模式	YES	YES	NO	YES	YES	YES
端子数量	84	84	84	100	100	100
最高工作温度	70 °C	70 °C	85 °C	70 °C	70 °C	70 °C
输出数据总线宽度	28	28	28	28	28	28
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	QCCJ	QCCJ	QCCJ	QFP	QFP	QFP
封装等效代码	LDCC84,1.2SQ	LDCC84,1.2SQ	LDCC84,1.2SQ	QFP100,.7X.9	QFP100,.7X.9	QFP100,.7X.9
封装形状	SQUARE	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	FLATPACK	FLATPACK	FLATPACK
电源	5 V	5 V	5 V	5 V	5 V	5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
最大压摆率	363 mA	363 mA	363 mA	363 mA	363 mA	363 mA
标称供电电压	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	J BEND	J BEND	J BEND	GULL WING	GULL WING	GULL WING
端子节距	1.27 mm	1.27 mm	1.27 mm	0.635 mm	0.635 mm	0.635 mm
端子位置	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
uPs/uCs/外围集成电路类型	DSP PERIPHERAL, DIGITAL FILTER	DSP PERIPHERAL, DIGITAL FILTER	DSP PERIPHERAL, DIGITAL FILTER	DSP PERIPHERAL, DIGITAL FILTER	DSP PERIPHERAL, DIGITAL FILTER	DSP PERIPHERAL, DIGITAL FILTER
Base Number Matches	1	1	1	1	1	1
ECCN代码	3A001.A.3	3A001.A.3	-	3A001.A.3	3A991.A.2	3A001.A.3
最大时钟频率	45.45 MHz	40.81 MHz	-	45.45 MHz	33.33 MHz	40.81 MHz
最大供电电压	5.25 V	5.25 V	-	5.25 V	5.25 V	5.25 V
最小供电电压	4.75 V	4.75 V	-	4.75 V	4.75 V	4.75 V

HSP43168JC-45

HSP43168JC-45概述

HSP43168JC-45规格参数

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