®
LY61256
Rev. 1.7
32K X 8 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Description
Initial Issue
Delete Icc1/ I
SB
Spec.
Adding Skinny P-DIP
Revised
STSOP Package Outline Dimension
Revised V
TERM
to V
T1
and V
T2
Revised Test Condition of I
SB1
/I
DR
Added LL Spec.
Revised Test Condition of I
CC
Revised
FEATURES
&
ORDERING INFORMATION
Lead free and green package available
to
Green package
available
Deleted T
SOLDER
in
ABSOLUTE MAXIMUN RATINGS
Added packing type in
ORDERING INFORMATION
Revised
PACKAGE OUTLINE DIMENSION
in page 10
Revised
ORDERING INFORMATION
in page 11
Revised
PACKAGE OUTLINE DIMENSION
in page 9
Issue Date
Jul.25.2004
Sep.21.2004
Aug.18.2005
Mar.26.2008
Feb.2.2009
Rev. 1.5
Apr.17.2009
Rev. 1.6
Rev. 1.7
May.7.2010
Aug.25.2010
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
®
LY61256
Rev. 1.7
32K X 8 BIT HIGH SPEED CMOS SRAM
GENERAL DESCRIPTION
The LY61256 is a 262,144-bit high speed CMOS
static random access memory organized as 32,768
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The LY61256 is well designed for high speed
system application. Easy expansion is provided by
using an active LOW Chip Enable(CE#). The active
LOW Write Enable(WE#) controls both writing and
reading of the memory.
The LY61256 operates from a single power
supply of 5V and all inputs and outputs are fully TTL
compatible
FEATURES
Fast access time : 8/10/12/15ns
Low power consumption:
Operating current : 110/100/90/80mA (TYP.)
Standby current : 1mA (TYP.)
2μA (TYP.) LL-version
Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data retention voltage : 2.0V (MIN.)
Green package available
Package : 28-pin 300 mil SOJ
28-pin 300 mil Skinny P-DIP
28-pin 8mm x 13.4mm STSOP
PRODUCT FAMILY
Product
Family
LY61256
LY61256(E)
LY61256(I)
LY61256(LL)
LY61256(LLE)
LY61256(LLI)
Operating
Temperature
0 ~ 70℃
-20 ~ 80℃
-40 ~ 85℃
0 ~ 70℃
-20 ~ 80℃
-40 ~ 85℃
Vcc Range
4.5 ~ 5.5V
4.5 ~ 5.5V
4.5 ~ 5.5V
4.5 ~ 5.5V
4.5 ~ 5.5V
4.5 ~ 5.5V
Speed
8/10/12/15ns
8/10/12/15ns
8/10/12/15ns
8/10/12/15ns
8/10/12/15ns
8/10/12/15ns
Power Dissipation
Standby(I
SB1,
TYP.) Operating(Icc,TYP.)
1mA
110/100/90/80mA
1mA
110/100/90/80mA
1mA
110/100/90/80mA
110/100/90/80mA
2μA(LL)
110/100/90/80mA
2μA(LL)
110/100/90/80mA
2μA(LL)
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
PIN DESCRIPTION
SYMBOL
A0 - A14
DQ0 – DQ7
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
A0-A14
DECODER
32Kx8
MEMORY ARRAY
CE#
WE#
OE#
V
CC
V
SS
DQ0-DQ7
I/O DATA
CIRCUIT
COLUMN I/O
CE#
WE#
OE#
CONTROL
CIRCUIT
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
®
LY61256
Rev. 1.7
32K X 8 BIT HIGH SPEED CMOS SRAM
PIN CONFIGURATION
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE#
A13
A8
A9
A11
OE#
A10
CE#
I/O8
I/O7
I/O6
I/O5
I/O4
OE#
A11
A9
A8
A13
WE#
Vcc
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE#
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
Skinny P-DIP/SOJ
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Voltage on V
CC
relative to V
SS
Voltage on any other pin relative to V
SS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
SYMBOL
V
T1
V
T2
T
A
T
STG
P
D
I
OUT
RATING
-0.5 to 6.5
-0.5 to V
CC
+0.5
0 to 70(C grade)
-20 to 80(E grade)
-40 to 85(I grade)
-65 to 150
1
50
UNIT
V
V
℃
℃
W
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
LY61256
LY61256
STSOP
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
H
L
L
L
OE#
X
H
L
X
WE#
X
H
H
L
I/O OPERATION
High-Z
High-Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB1
I
CC
I
CC
I
CC
H = V
IH
, L = V
IL
, X = Don't care.
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
®
LY61256
Rev. 1.7
32K X 8 BIT HIGH SPEED CMOS SRAM
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
PARAMETER
Supply Voltage
V
CC
*1
Input High Voltage
V
IH
*2
Input Low Voltage
V
IL
Input Leakage Current
I
LI
V
CC
≧
V
IN
≧
V
SS
Output Leakage
V
CC
≧
V
OUT
≧
V
SS
,
I
LO
Current
Output Disabled
Output High Voltage
V
OH
I
OH
= -4mA
Output Low Voltage
V
OL
I
OL
= 8mA
Average Operating
Power supply Current
Standby Power
Supply Current
I
CC
Cycle time = Min.
CE# = V
IL
, I
I/O
= 0mA
Others at V
IL
or V
IH
-8
-10
-12
-15
Normal
MIN.
4.5
2.4
- 0.5
-1
-1
2.4
-
-
-
-
-
-
-
TYP.
5.0
-
-
-
-
-
-
110
100
90
80
1
2
*4
MAX.
5.5
V
CC
+0.5
0.8
1
1
-
0.4
190
180
160
140
5
50
UNIT
V
V
V
µA
µA
V
V
mA
mA
mA
mA
mA
µA
I
SB1
CE#
≧
V
CC
- 0.2V,
CE#
≧
V
CC
- 0.2V,
LL
Others at 0.2V or V
CC
-0.2V
Notes:
1. V
IH
(max) = V
CC
+ 3.0V for pulse width less than 10ns.
2. V
IL
(min) = V
SS
- 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at V
CC
= V
CC
(TYP.) and T
A
= 25℃
CAPACITANCE
(T
A
= 25
℃
, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to V
CC
- 0.2V
3ns
1.5V
C
L
= 30pF + 1TTL, I
OH
/I
OL
= -4mA/8mA
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
®
LY61256
Rev. 1.7
32K X 8 BIT HIGH SPEED CMOS SRAM
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM. LY61256-8 LY61256-10 LY61256-12 LY61256-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
t
RC
8
-
10
-
12
-
15
-
ns
t
AA
-
8
-
10
-
12
-
15
ns
t
ACE
-
8
-
10
-
12
-
15
ns
t
OE
-
4
-
5
-
6
-
7
ns
t
CLZ
*
2
-
2
-
3
-
4
-
ns
t
OLZ
*
0
-
0
-
0
-
0
-
ns
t
CHZ
*
-
4
-
5
-
6
-
7
ns
t
OHZ
*
-
4
-
5
-
6
-
7
ns
t
OH
3
-
3
-
3
-
3
-
ns
SYM. LY61256-8 LY61256-10 LY61256-12 LY61256-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
t
WC
8
-
10
-
12
-
15
-
ns
t
AW
6.5
-
8
-
10
-
12
-
ns
t
CW
6.5
-
8
-
10
-
12
-
ns
t
AS
0
-
0
-
0
-
0
-
ns
t
WP
6.5
-
8
-
9
-
10
-
ns
t
WR
0
-
0
-
0
-
0
-
ns
t
DW
5
-
6
-
7
-
8
-
ns
t
DH
0
-
0
-
0
-
0
-
ns
t
OW
*
1.5
-
2
-
3
-
4
-
ns
t
WHZ
*
-
5
-
6
-
7
-
8
ns
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
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