INTEGRATED CIRCUITS
SA5224
FDDI fiber optic postamplifier
Product specification
Replaces datasheet NE/SA5224 of 1995 Apr 26
IC19 Data Handbook
1998 Oct 07
Philips
Semiconductors
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
SA5224
DESCRIPTION
The SA5224 is a high-gain limiting amplifier that is designed to
process signals from fiber optic preamplifiers. Capable of operating
at 125Mb/s, the chip is FDDI compatible and has input signal
level-detection with a user-adjustable threshold. The DATA and
LEVEL-DETECT outputs are differential for optimum noise margin
and ease of use. Also available is the SA5225 which is an ECL 10K
version of the SA5224.
PIN DESCRIPTION
D Package
CAZN
CAZP
1
2
16
15
14
13
12
11
10
9
V
SET
V
REF
V
CCE
D
OUT
D
OUT
GND
E
ST
ST
GND
A
3
D
IN
4
D
IN
5
V
CCA
6
CF 7
JAM
8
FEATURES
•
Wideband operation: 1.0kHz to 120MHz typical
•
Applicable in 155Mb/s OC3/SONET receivers
•
Operation with single +5V or –5.2V supply
•
Differential 100k ECL outputs
•
Programmable input signal level-detection
•
Fully differential for excellent PSRR to 1GHz
SD00374
Figure 1. Pin Configuration
APPLICATIONS
•
FDDI
•
Data communication in noisy industrial environments
•
LANs
TEMPERATURE RANGE
–40 to +85
°
C
ORDER CODE
SA5224D
DWG #
SOT109-1
ORDERING INFORMATION
DESCRIPTION
16-Pin Plastic Small Outline (SO) package
BLOCK DIAGRAM
V
CCA
(6)
C
AZP
C
AZN
(2)
(1)
V
CCE
(16)
D
IN
(4)
D
IN
(5)
LIMITING
AMPLIFIER
ECL
BUFFER
(13) D
OUT
(12) D
OUT
JAM
BUFFER
(8) JAM
V
REF
(15)
REFERENCE
LEVEL
DETECTOR
SD
BUFFER
(9) ST
(10) ST
V
SET
(16)
(3)
GND
A
(7)
C
F
(11)
GND
E
SD00375
Figure 2. Block Diagram
1998 Oct 07
2
853-1594 20141
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
SA5224
PIN DESCRIPTIONS
PIN NO.
1
2
3
4
5
6
7
8
NAME
C
AZN
C
AZP
GND
A
D
IN
D
IN
V
CCA
C
F
JAM
FUNCTION
Auto-zero capacitor pin. Connecting a capacitor between this pin and C
AZP
will cancel the offset voltage of the
limiting amplifier.
Auto-zero capacitor pin. Connecting a capacitor between this pin and C
AZN
will cancel the offset voltage of the
limiting amplifier.
Analog GND pin. Connect to ground for +5V upshifted ECL operation. Connect to –5.2V for standard ECL
operation. Must be at same potential as GND
E
(Pin 11).
Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to D
IN
(Pin 5).
Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to D
IN
(Pin 4).
Analog power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground for standard
ECL operation. Must be at same potential as V
CCE
(Pin 14).
Filter capacitor for level detector. Capacitor should be connected between this pin and V
CCA
.
This ECL-compatible input controls the output buffers D
OUT
and D
OUT
(Pins 12 and 13). When an ECL LOW signal
is applied, the outputs will follow the input signal. When an ECL HIGH signal is applied, the D
OUT
and D
OUT
pins
will latch into LOW and HIGH states, respectively. When left unconnected, this pin is actively pulled-low (JAM OFF).
Input signal level-detect STATUS. This ECL output is high when the input signal is below the user programmable
threshold level.
ECL compliment of ST (Pin 9).
Digital GND pin. Connect to ground for +5V upshifted ECL operation. Connect to a negative supply for normal ECL
operation. Must be at the same potential as GND
A
(Pin 3).
ECL-compatible output. Nominal level is V
CCE
–1.3V. When JAM is HIGH, this pin will be forced into an ECL HIGH
condition. Complimentary to D
OUT
(Pin 13).
ECL-compatible output. Nominal level is V
CCE
–1.3V. When JAM is HIGH, this pin will be forced into an ECL LOW
condition. Complimentary to D
OUT
(Pin 12).
Digital power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground during normal
ECL operation. Must be at the same potential as V
CCA
(Pin 6).
Reference voltage for threshold level voltage divider. Nominal value is approximately 2.64V.
Input threshold level setting circuit. This input can come from a voltage divider between V
REF
and GND
A
.
9
10
11
12
13
14
15
16
ST
ST
GND
E
D
OUT
D
OUT
V
CCE
V
REF
V
SET
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
T
A
T
J
T
STG
P
D
Power supply (V
CC
- GND)
Operating ambient
Operating junction
Storage
Power dissipation, T
A
= 25°C (still air)
1
16-pin Plastic SO
PARAMETER
RATING
6
–45 to +85
–55 to +150
–65 to +150
1100
UNITS
V
°
C
°
C
°
C
mW
NOTE:
1. Maximum dissipation is determined by the ambient temperature and the thermal resistance,
θ
JA
: 16-pin SO:
θ
JA
= 110°C/W
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
T
A
T
J
Supply voltage
Ambient temperature ranges
Junction temperature ranges
PARAMETER
RATING
4.5 to 5.5
–40 to +85
–40 to +110
UNITS
V
°
C
°
C
1998 Oct 07
3
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
SA5224
DC ELECTRICAL CHARACTERISTICS
Min and Max limits apply over operating temperature at V
CC
= 5V
±10%,
unless otherwise specified. Typical data apply at T
A
= 25
°
C and V
CC
=
+5V.
SYMBOL
PARAMETER
Input signal voltage
single-ended
differential
Input offset voltage
2
Input RMS noise
2
Input level-detect programmability
single-ended
Level-detect hysteresis
V
CCA
+ V
CCE
supply current
JAM input current
Maximum logic high
1
Minimum logic high
1
Maximum logic
low
1
–1.870
high
1
–1.165
–1.490
Minimum logic low
1
Minimum input for JAM =
–1.055
–1.620
V
IN
= 200kHz square
wave
No ECL loading
Pin 8 = 0V
–10
2
4
5
27
TEST CONDITIONS
SA5224
Min
.002
.004
Typ
Max
1.5
3.0
50
60
12
6
35
10
–0.880
UNIT
V
IN
V
OS
V
N
V
TH
V
HYS
I
CC
I
INL
V
OHMAX
V
OHMIN
V
OLMAX
V
OLMIN
V
IH
V
P-P
µV
µV
mV
P-P
dB
mA
µA
V
DC
V
DC
V
DC
V
DC
V
DC
V
DC
V
IL
Maximum input for JAM = low
1
NOTES:
1. These ECL specifications are referenced to the V
CCE
rail and apply for T
A
= 0°C to 85°C.
2. Guaranteed by design.
AC ELECTRICAL CHARACTERISTICS
Typical data apply at T
A
= 25
°
C and V
CC
= +5V. Min and Max limits apply for 4.5
≤
V
CC
≤
5.5V.
SYMBOL
BW
1
BW
2
R
IN
C
IN
tr, tf
t
PWD
R
AZ
R
F
t
LD
PARAMETER
Lower –3dB bandwidth
Upper –3dB bandwidth
Input resistance
Input capacitance
ECL output
3
risetime,
falltime
Pin 4 or 5
Pin 4 or 5
R
L
= 50Ω
To V
CCE
- 2V
20-80%
Pin 1 or 2
Pin 7
C
F
= 0
TEST CONDITIONS
C
AZ
= 0.1µF
Min
0.5
90
2.9
Typ
1.0
120
4.5
Max
1.5
150
7.6
2.5
1.2
2.2
0.3
155
14
0.5
250
24
1.0
423
41
2.0
UNIT
kHz
MHz
kΩ
pF
ns
ns
P-P
kΩ
kΩ
µs
Pulsewidth distortion
Auto zero output resistance
Level-detect filter resistance
Level-detect time constant
NOTES:
1. Both outputs should be terminated identically to minimize differential feedback to the device inputs on a PC board or substrate.
1998 Oct 07
4
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
SA5224
NE5212
NE5224
CLOCK
RECOVERY
&
RETIMING
ECL data outputs if the input is below a set threshold. This prevents
the outputs from reacting to noise in the absence of a valid input
signal, and insures that data will only be transmitted when the input
signal-to-noise ratio is sufficient for low bit-error-rate system
operation. Complimentary ECL flags (ST and STB) indicate whether
the input signal is above or below the desired threshold level.
Figure 6 shows a simplified block diagram of the SA5224
level-detect system. The input signal is amplified and rectified
before being compared to a programmable reference. A filter is
included to prevent noise spikes from triggering the level-detector.
This filter has a nominal 1µs time constant, and additional filtering
can be achieved by using an external capacitor (CF) from Pin 7 to
V
CCA
(the internal driving impedance is nominally 24k). The
resultant signal is then compared to a programmable level, V
SET
,
which is set by an internal voltage reference (2.64V) and an external
resistor divider (R1 and R2). The value of R1 + R2 should be
maintained at approximately 5k.
HYST
SD00376
Figure 3. Typical Fiber Optic Receiving System
INPUT BIASING
The DATA INPUT pins (4 and 5) are DC biased at approximately
2.9V by an internal reference generator. The SA5224 can be DC
coupled, but the driving source must operate within the allowable
1.4V to 4.4V input signal range (for V
CC
= 5V). If AC coupling is
used to remove any DC compatibility requirement, the coupling
capacitors C1 and C2 must be large enough to pass the lowest input
frequency of interest. For example, .001µF coupling capacitors
react with the internal 4.5k input bias resistors to yield a lower –3dB
frequency of 35kHz. This then sets a limit on the maximum number
of consecutive “1”s or “0”s that can be sensed accurately at the
system data rate. Capacitor tolerance and resistor variation (2.9k to
7.6k) must be included for an accurate calculation.
V
TL
(OFF)
V
TH
(ON)
SD00377
Figure 4.
AUTO-ZERO CIRCUIT
Figure 5 also shows the essential details of the auto-zero circuit. A
feedback amplifier (A4) is used to cancel the offset voltage of the
forward signal path, so the input to the internal ECL comparator (A6)
is at its toggle point in the absence of any input signal. The time
constant of the cancelling circuitry is set by an external capacitor
(C
AZ
) connected between Pins 1 and 2. The formula for the lower
–3dB frequency is:
150
f
*3dB
+
2p
@
R
AZ
@
C
AZ
where R
AZ
is the internal driving impedance which can vary from
155k to 423k over temperature and device fabrication limits. The
input coupling time constant must also be considered in determining
the lower frequency response of the SA5224.
The circuit is designed to operate accurately over a differential
2-12mV
P-P
square-wave input level detect range. This level,
V
SET
/100, is the average of V
TH
and V
TL
.
Nominal hysteresis of 5dB is provided by the complimentary ECL
V
SET
V
SET
V
TL
+
V
TH
+
139 and
78 . For
output comparator yielding
example, with V
SET
= 1.2V, a 15.4mV
P-P
square-wave differential
input will drive the ST pin high, and an input level below 8.6mV
P-P
will drive the ST pin low.
Since a “JAM” function is provided (Pin 8) and can force the data
outputs to a predetermined state (D
OUT
= LOW, D
OUT
= HIGH), the
ST and JAM pins can be connected together to automatically
disable signal transmission when the chip senses that the input
signal is below the desired threshold. JAM (Pin 8) low enables the
Data Outputs. ST will be in a high ECL state for input signals below
threshold.
INPUT SIGNAL LEVEL-DETECTION
The SA5224 allows for user programmable input signal
level-detection and can automatically disable the switching of its
C
AZ
V
BIAS
R
IN
4.5kΩ
C1
–
DATA IN
C2
D
IN
D
INB
A1
+
R
IN
4.5kΩ
R
AZ
250kΩ
A4
R
AZ
250kΩ
D
OUT
A3
A6
D
OUTB
ECL 100k
DATA OUT
SD00378
Figure 5. SA5224 Forward Gain Path Including Auto-Zero
1998 Oct 07
5
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