Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
DESCRIPTION
The NE568A is a monolithic phase-locked loop (PLL) which
operates from 1Hz to frequencies in excess of 150MHz and features
an extended supply voltage range and a lower temperature
coefficient of the V
CO
center frequency in comparison with its
predecessor, the NE 568. The NE568A is function and
pin-compatible with the NE568, requiring only minor changes in
peripheral circuitry (see Figure 3). Temperature compensation
network is different, no resistor on Pin 12, needs to be grounded and
Pin 13 has a 3.9kΩ resistor to ground. Timing cap, C
2
, is different
and for 70MHz operation with temperature compensation network
should be 16pF, not 34pF as was used in the NE568. The NE568A
has the following improvements: ESD protected; extended V
CC
range from 4.5V to 5.5V; operating temperature range -55 to 125°C
(see Signetics Military 568A data sheet); less layout sensitivity; and
lower T
C
of VCO (center frequency). The integrated circuit consists
of a limiting amplifier, a current-controlled oscillator (ICO), a phase
detector, a level shift circuit, V/I and I/V converters, an output buffer,
and bias circuitry with temperature and frequency compensating
characteristics. The design of the NE568A is particularly well-suited
for demodulation of FM signals with extremely large deviation in
systems which require a highly linear output. In satellite receiver
applications with a 70MHz IF, the NE568A will demodulate
±20%
deviations with less than 1.0% typical non-linearity. In addition to
high linearity, the circuit has a loop filter which can be configured
with series or shunt elements to optimize loop dynamic
performance. The NE568A is available in 20-pin dual in-line and
20-pin SO (surface mounted) plastic packages.
PIN CONFIGURATION
D, N Packages
V
CC2
1
GND
2
2
GND
1
3
TCAP1
TCAP2
GND1
4
5
6
20
19
18
17
16
LF1
LF2
LF3
LF4
FREQ ADJ
15 OUT
FILT
14
V
OUT
V
CC1
7
REFBYP
PNPBYP
8
9
13 TC
ADJ2
12 TC
ADJ1
11
V
IN
INPBYP 10
TOP VIEW
SR01037
•
Series or shunt loop filter component capability
•
External loop gain control
•
Temperature compensated
•
ESD protected
1
APPLICATIONS
Figure 1. Pin Configuration
FEATURES
•
Operation to 150MHz
•
High linearity buffered output
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic Small Outline Large (SOL) Package
20-Pin Plastic Dual In-Line Package (DIP)
20-Pin Plastic Small Outline Large (SOL) Package
20-Pin Plastic Dual In-Line Package (DIP)
•
Satellite receivers
•
Fiber optic video links
•
VHF FSK demodulators
•
Clock Recovery
TEMPERATURE RANGE
0 to +70°C
0 to +70°C
-40 to +85°C
-40 to +85°C
ORDER CODE
NE568AD
NE568AN
SA568AD
SA568AN
DWG #
SOT163-1
SOT146-1
SOT163-1
SOT146-1
BLOCK DIAGRAM
LF1
20
LF2
19
LF3
18
LF4
17
FREQ ADJ
16
OUT
FILT
15
V
OUT
14
TC
ADJ2
13
TC
ADJ1
12
V
IN
11
LEVEL SHIFT
OUT
BUF
TCADJ
BIAS
LEVEL SHIFT
V/I
CONVERTER
PHASE
DETECTOR
I/V
CONVERTER
AMP
NOTE:
Pins 4 and 5 can tolerate
1000V only, and all other
pins, greater than 2000V
for ESD (human body
model).
ICO
1
V
CC2
2
GND
2
3
GND
1
4
TCAP1
5
TCAP2
6
GND1
7
V
CC1
8
REFBYP
9
PNPBYP
10
INPBYP
SR01038
Figure 2. Block Diagram
1996 Feb 1
1
853-1558 16328
Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
T
J
T
STG
P
DMAX
θ
JA
Supply voltage
Junction temperature
Storage temperature range
Maximum power dissipation
Thermal resistance
PARAMETER
RATING
6
+150
-65 to +150
400
80
UNITS
V
°C
°C
mW
°C/W
ELECTRICAL CHARACTERISTICS
The elctrical characteristics listed below are actual tests (unless
otherwise stated) performed on each device with an automatic IC
tester prior to shipment. Performance of the device in automated
test set-up is not necessarily optimum. The NE568A is
layout-sensitive. Evaluation of performance for correlation to the
data sheet should be done with the circuit and layout of Figures 3, 4,
and 5 with the evaluation unit soldered in place. (Do not use a
socket!)
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5V; T
A
= 25°C; f
O
= 70MHz, Test Circuit Figure 3, f
IN
= -20dBm, R
4
= 3.9kΩ, unless otherwise specified.
LIMITS
SYMBOL
V
CC
I
CC
PARAMETER
Supply voltage
Supply current
TEST CONDITIONS
MIN
4.5
NE/SA568A
TYP
5
54
MAX
5.5
70
V
mA
UNITS
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
f
OSC
Maximum oscillator operating frequency
3
Input signal level
BW
Demodulated bandwidth
Non-linearity
5
Lock range
2
Capture range
2
TC of f
O
R
IN
Input resistance
4
Output impedance
Demodulated V
OUT
AM rejection
Distribution
6
Drift with supply
Dev =
±20%
of f
O
measured at
Pin 14
V
IN
= -20dBm (30% AM)
referred to
±20%
deviation
Centered at 70MHz, R
2
=
1.2kΩ, C
2
= 16pF, R
4
= 3.9kΩ
(C
2
+ C
STRAY
= 20pF)
4.5V to 5.5V
-15
0.40
Dev =
±20%,
Input = -20dBm
Input = -20dBm
Input = -20dBm
Figure 3
1
6
0.52
50
±25
±20
150
50
–20
1
f
O
/7
1.0
±35
±30
100
4.0
2000
+10
NE/SA568A
TYP
MAX
MHz
mV
P-P
dBm
MHz
%
% of f
O
% of f
O
ppm/°C
kΩ
Ω
V
P-P
dB
UNITS
f
O
f
O
0
2
+15
%
%/V
NOTE:
1. Signal level to assure all published parameters. Device will continue to function at lower levels with varying performance.
2. Limits are set symmetrical to f
O
. Actual characteristics may have asymmetry beyond the specified limits.
3. Not 100% tested, but guaranteed by design.
4. Input impedance depends on package and layout capacitances. See Figures 6 and 5.
5. Linearity is tested with incremental changes in inupt frequency and measurement of the DC output voltage at Pin 14 (V
OUT
). Non-linearity is
then calculated from a straight line over the deviation range specified.
6. Free-running frequency is measured as feedthrough to Pin 14 (V
OUT
) with no input signal applied.
1996 Feb 1
2
Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
1
C1
2
V
CC2
GND2
LF1
20
LF2
19
R1
C10
3
GND1
LF3
18
C9
4
R
FC1
C2
5
TCAP1
LF4
17
R2
TCAP2
FREQADJ
16
6
C8
7
GND1
OUTFILT
15
C11
V
OUT
14
V
CC1
V
OUT
13
REFBYP
TCADJ2
TCADJ1
12
C12
R3
C3
V
CC
C5
C6
8
R
FC2
C4
9
PNPBYP
R4
10
C7
INPBYP
11
V
IN
C13
R5
V
IN
SR01039
Figure 3. Test Circuit for AC Parameters
FUNCTIONAL DESCRIPTION
The NE568A is a high-performance phase-locked loop (PLL). The
circuit consists of conventional PLL elements, with special circuitry
for linearized demodulated output, and high-frequency performance.
The process used has NPN transistors with f
T
> 6GHz. The high
gain and bandwidth of these transistors make careful attention to
layout and bypass critical for optimum performance. The
performance of the PLL cannot be evaluated independent of the
layout. The use of the application layout in this data sheet and
surface-mount capacitors are highly recommended as a starting
point.
The input to the PLL is through a limiting amplifier with a gain of 200.
The input of this amplifier is differential (Pins 10 and 11). For
single-ended applications, the input must be coupled through a
DC-blocking capacitor with low impedance at the frequency of
interest. The single-ended input is normally applied to Pin 11 with
Pin 10 AC-bypassed with a low-impedance capacitor. The input
impedance is characteristically slightly above 500Ω. Impedance
match is not necessary, but loading the signal source should be
avoided. When the source is 50 or 75Ω, a DC-blocking capacitor is
usually all that is needed.
Input amplification is low enough to assure reasonable response
time in the case of large signals, but high enough for good AM
rejection. After amplification, the input signal drives one port of a
multiplier-cell phase detector. The other port is driven by the
current-controlled oscillator (ICO). The output of the phase
comparator is a voltage proportional to the phase difference of the
input and ICO signals. The error signal is filtered with a low-pass
filter to provide a DC-correction voltage, and this voltage is
converted to a current which is applied to the ICO, shifting the
frequency in the direction which causes the input and ICO to have a
90° phase relationship.
The oscillator is a current-controlled multivibrator. The current
control affects the charge/discharge rate of the timing capacitor. It is
common for this type of oscillator to be referred to as a
voltage-controlled oscillator (VCO), because the output of the phase
comparator and the loop filter is a voltage. To control the frequency
of an integrated ICO multivibrator, the control signal must be
conditioned by a voltage-to-current converter. In the NE568A,
special circuitry predistorts the control signal to make the change in
frequency a linear function over a large control-current range.
The free-running frequency of the oscillator depends on the value of
the timing capacitor connected between Pins 4 and 5. The value of
the timing capacitor depends on internal resistive components and
current sources. When R
2
= 1.2kΩ and R
4
= 0Ω, a very close
approximation of the correct capacitor value is:
0.0014
C*
+
F
f
O
where
C *
+
C
2
)
C
STRAY
The temperature-compensation resistor, R
4
, affects the actual value
of capacitance. This equation is normalized to 70MHz. See 10 for
correction factors.
The loop filter determines the dynamic characteristics of the loop. In
most PLLs, the phase detector outputs are internally connected to
the ICO inputs. The NE568A was designed with filter output to input
connections from Pins 20 (φ DET) to 17 (ICO), and Pins 19 (φ DET)
to 18 (ICO) external. This allows the use of both series and shunt
loop-filter elements. The loop constratints are:
K
O
+
0.12V Radian (Phase Detector Constant)
K
O
+
4.2
@
10
9
Radians
(ICO Constant) at 70MHz
V
–sec
The loop filter determines the general characteristics of the loop.
Capacitors C
9
, C
10
, and resistor R
1
, control the transient output of
the phase detector. Capacitor C
9
suppresses 70MHz feedthrough
by interaction with 100Ω load resistors internal to the phase
detector.
1996 Feb 1
3
Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
C
9
+
1
F
2p (50) (f
O
)
Parts List and Layout 70MHz Application NE568AN
C
1
C
2 1
C
2 2
C
3
C
4
C
5
C
6
C
7
C
8
C
9
C
10
C
11
C
12
C
13
R
1
R
2
100nF
18pF
16pF
100nF
100nF
6.8µF
100nF
100nF
100nF
47pF
560pF
47pF
100nF
100nF
27Ω
1.2kΩ
43Ω
3.9kΩ
50Ω
10µH
10µH
±10%
±10%
±10%
±10%
±10%
±10%
±2%
±2%
±10%
±10%
±10%
±10%
±10%
±10%
±2%
±2%
±2%
±10%
±10%
±10%
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic chip
Tantalum
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic
CR32
Trim pot
Ceramic
CR32
Ceramic
CR32
Ceramic
CR32
chip
chip
chip
1/4W
1/4W
1/4W
chip
50V
50V
0805
50V
50V
35V
50V
50V
50V
50V
50V
50V
50V
50V
1/4W
At 70MHz, the calculated value is 45pF. Empirical results with the
test and application board were improved when a 47pF capacitor
was used.
The natural frequency for the loop filter is set by C
10
and R
1
. If the
center frequency of the loop is 70MHz and the full demodulated
bandwidth is desired, i.e., f
BW
= f
O
/7 = 10MHz, and a value for R
1
is
chosen, the value of C
10
can be calculated.
C
10
+
Also,
C
11
1
+
2p350Wf
BW(Hz)
1
F
2p R
1
f
BW
This capacitance determines the signal bandwidth of the output
buffer amplifier. (For further inofrmation see Philips application note
AN1881 “The NE568A Phase Locked Loop as a Wideband Video
Demodulator”.
Parts List and Layout 40MHz Application NE568AD
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
8
C
9
C
10
C
11
C
12
C
13
R
1
R
2
R
3
3
1
R
3 3
R
4 4
R
5 3
RFC
1
RFC
2
100nF
18pF
16pF
100nF
100nF
6.8µF
100nF
100nF
100nF
47pF
560pF
47pF
100nF
100nF
27Ω
1.2kΩ
43Ω
3.9kΩ
50Ω
5
±10%
±2%
±2%
±10%
±10%
±10%
±10%
±10%
±10%
±2%
±2%
±2%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
Ceramic chip
Ceramic chip
Ceramic ORChip
Ceramic chip
Ceramic chip
Tantalum
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic chip
Ceramic chip
Chip CR32
Trim pot
Chip CR32
Chip CR32
Chip CR32
Surface mount
Surface mount
1206
0805
1206
1206
35V
1206
1206
1206
0805 or 1206
0805 or 1206
0805 or 1206
1206
1206
1/4W
1/4W
1/4W
1/4W
C
2 2
Surface mount
Surface mount
NOTES:
1. 18pF with Pin 12 ground and Pin 13 no connect (open).
2. C
2
+ C
STRAY
= 16pF for temperature-compensated configuration
with R
4
= 3.9kΩ.
3. For 50Ω setup. R
1
= 62Ω, R
3
= 75Ω for 75Ω application.
4. For test configuration R
4
= 0Ω (GND) and C
2
= 18pF.
R
4 4
R
5 3
RFC
1
RFC
25
10µH
10µH
NOTES:
1. 18pF with Pin 12 ground and Pin 13 no connect (open).
2. C
2
+ C
STRAY
= 16pF for temperature-compensated configuration
with R
4
= 3.9kΩ.
3. For 50Ω setup. R
1
= 62Ω, R
3
= 75Ω for 75Ω application.
4. For test configuration R
4
= 0Ω (GND) and C
2
= 18pF.
5. 0Ω chip resistors (jumpers) may be substituted with minor degra-
dation of performance.
1996 Feb 1
4
Philips Semiconductors
Product specification
150MHz phase-locked loop
NE/SA568A
NE568A
KT10/89
GND
V
CC
V
OUT
V
IN
SR01040
Figure 4. N Package Layout (Not Actual Size)
GND
V
CC
SIGNETICS
NE568A SO
OUTPUT
INPUT
SR01041
Figure 5. D Package Layout (Not Actual Size)
1.25E3
1.25E3
1.0E3
1.0E3
Z
IN
Z IN
Ω
750.0
Z
IN
Z IN
Ω
750.0
500.0
500.0
R
IN
250.0
250.0
0.0
1.0
10.0
100.0
0.0
1.0
10.0
100.0
1.0E3
FREQUENCY (MHz)
SR01042
FREQUENCY (MHz)
SR01043
Figure 6. NE568A Input Impedance With CP = 0.5pF 20-Pin SO
Package
Figure 7. NE568A Input Impedance WithCP = 1.49pF 20-Pin
Dual In-Line Plastic Package
1996 Feb 1
5
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