INTEGRATED CIRCUITS
SA5753
Audio processor — filter and control
section
Product specification
Replaces data of 1995 July 7
IC17 Data Handbook
1997 Nov 07
Philips
Semiconductors
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
DESCRIPTION
The SA5753 is a high performance low power CMOS audio signal
processing system especially designed to meet the requirements for
small size and low voltage operation of hand-held equipment. The
SA5753 subsystem includes complementary transmit/receive voice
band (300-3000Hz), switched capacitor bandpass filters with
pre-emphasis and de-emphasis respectively, a transmit low pass
filter, peak deviation limiter for transmit, digitally controlled
attenuators for signal level and volume control, audio path mute
switches, a programmable DTMF generator, power-down circuitry
for low current standby, power-on reset capability, and an I
2
C
interface. When the SA5753 is used with an SA5752 (companding
function), the complete audio processing system of an AMPS,
TACS, NAMPS or NTACS cellular telephone is easily implemented.
The system also meets the requirements of the proposed NAMPS or
NTACS specification, and can be used in cordless telephone
applications.
The SA5753 can be operated without the I
2
C bus interface by
pulling DFT (Pin 13) HIGH.
PIN CONFIGURATION
DK Package
TXBF
IN
1
TXBF
OUT
2
PREMP
IN
3
V
DD
4
20 TX
OUT
19 DATA
IN
18 TX MUTE
17 SDA
16 SCL
VOX
CTL
5
HPDN 6
DEMP
OUT
7
AUDIO
IN
8
SPKR
OUT
9
EAR
OUT
10
SA5753
15 GND
14 CLK
IN
13 DFT
12 RX MUTE
11
RX DEMOD
IN
SR00666
Figure 1. Pin Configuration
BENEFITS
FEATURES
•
Very compact application
•
Long battery life in portable equipment
•
Complete cellular audio function with the SA5752
APPLICATIONS
•
Cellular radio
•
Mobile communications
•
High performance cordless telephones
•
2-way radio
•
Low 3V supply
•
Miniature SSOP package
•
Low power
•
High performance
•
Built-in programmable DTMF generator
•
Built-in digitally controlled attenuators for modulation and volume
control
•
Built-in peak-deviation limiter
•
I
2
C Bus controlled
•
Power-on reset
•
Power down capability
•
Programmable mute control
•
Meets AMPS/TACS/NAMPS/NTACS requirements
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic Shrink Small Outline Package (SSOP)
TEMPERATURE RANGE
-40 to +85°C
ORDER CODE
SA5753DK
DWG #
SOT266-1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
IN
T
A
Power supply voltage range
Voltage applied to any other pin
Storage temperature
Ambient operating temperature
PARAMETER
RATING
-0.3 to 6
-0.3 to V
DD
+0.3
-65 to +150
-40 to +85
UNIT
V
V
o
C
°
C
1997 Nov 07
2
853-1722 18666
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
PIN DESCRIPTIONS
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SYMBOL
TXBF
IN
TXBF
OUT
PREMP
IN
V
DD
VOX
CTL
HPDN
DEMP
OUT
AUDIO
IN
SPKR
OUT
EAR
OUT
RX DEMOD
IN
RX MUTE
DFT
CLK
IN
GND
SCL
SDA
TX MUTE
DATA
IN
TX
OUT
Transmit bandpass filter input
Transmit bandpass filter output
Pre-emphasis input
Positive supply
Vox control output
Power-down I/O
De-emphasis output
Audio input
Audio output to speaker
Audio output to earpiece
Rx demodulated audio signal input
RX audio signal mute input
Default input, non-I
2
C or stand-alone operation
Clock input (1.2MHz)
Ground
I
2
C serial clock line
I
2
C serial data line
Tx audio signal mute input
Data input
Transmit output
DESCRIPTION
1997 Nov 07
3
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
DC ELECTRICAL CHARACTERISTICS
T
A
= 25
o
C, V
DD
= +3.3V, unless otherwise specified. See test circuit, Figure 2.
SYMBOL
V
DD
I
DD
PARAMETER
Power supply voltage
Supply current
Input current high
TX MUTE, RX MUTE, HPDN
DFT
Input current low
TX MUTE, RX MUTE,
HPDN, DFT
Input voltage high
Input voltage low
Operating
IDLE
Power Down (PWDN)
V
IN
= V
DD
–10
0
V
IN
= GND
–30
–10
0.7V
DD
0
–10
0
0
+10
V
DD
0.3V
DD
0
+10
+10
+30
TEST CONDITIONS
LIMITS
MIN
3.0
TYP
3.3
1.7
600
200
MAX
5.5
UNIT
V
mA
µA
µA
µA
µA
µA
µA
V
V
I
IH
I
IL
V
IH
V
IL
AC ELECTRICAL CHARACTERISTICS
T
A
= 25
o
C, V
DD
= +3.3V. See test circuit, Figure 2. Clock frequency = 1.2MHz; test level = 0dBV = 77.5mV
RMS
= -20dBm, unless otherwise
specified. All gain control blocks (Attenuators) = 0dB gain, NAMPS and VCO bits set to 0.
SYMBOL
PARAMETER
RX BPF anti alias rejection
RX BPF input impedance
RX BPF gain with de-emphasis
RX BPF gain with de-emphasis
RX BPF gain with de-emphasis
RX BPF gain with de-emphasis
RX BPF gain with de-emphasis
RX BPF noise with de-emphasis
RX dynamic range
DEMP
OUT
output impedance
DEMP
OUT
output swing (1%)
SPKR
OUT
ouput swing (1%)
EAR
OUT
output swing (1%)
SPKR
OUT
noise / EAR
OUT
noise
CLK
IN
high
CLK
IN
low
TX BPF anti alias rejection
TX BPF input impedance
TX BPF noise
TX LPF gain
TX LPF gain with pre-emphasis
TX LPF gain with pre-emphasis
TX LPF gain with pre-emphasis
TX LPF gain with pre-emphasis
TX LPF gain with pre-emphasis
TX LPF gain with pre-emphasis
TX overall gain
TX overall gain
TX overall gain
f > 50kHz
f = 3kHz
300 - 3000kHz
f = 5.9kHz
f = 1kHz, 0dBV
f = 100Hz
f = 300Hz
f = 3kHz
f = 5900Hz
f = 9kHz
1kHz
100Hz
300Hz
-11.5
2.1
0
40
100
200
-39
2.43
-19
-10.45
9.14
-28
-48
2.43
-58
-10.4
-44
-8.5
-36
f= 1kHz
f = 1kHz
f = 100Hz
f = 300Hz
f = 3kHz
f = 5.9kHz
300Hz-3kHz
with deemphasis
f = 1kHz
2kΩ to V
DD/2
; f = 1kHz
50kΩ toV
DD/2
; f = 1kHz
50kΩ to V
DD/2;
f = 1kHz
V
DD
-1
V
DD
-1
2.4
2.4
2.4
200
3.0
1.0
8.5
-11.5
-1.0
TEST CONDITIONS
LIMITS
MIN
TYP
40
100
0
-30
9.6
-10.0
-58
200
80
40
11.5
-8.5
1.0
MAX
UNIT
dB
kΩ
dB
dBm0
dBm0
dBm0
dBm0
µV
RMS
dB
Ω
V
P-P
V
P-P
V
P-P
µV
RMS
V
V
dB
KΩ
µV
RMS
dBm0
dB
dBm0
dBm0
dBm0
dBm0
dBm0
dB
dBm0
dBm0
1997 Nov 07
4
Philips Semiconductors
Product specification
Audio processor – filter and control section
SA5753
AC ELECTRICAL CHARACTERISTICS
(continued)
SYMBOL
TX overall gain
TX overall gain
TX BPF dynamic range
PREMP
IN
input impedance
TX
OUT
Slew rate
Output impedance
Output swing (limiting)
Output swing (1% THD)
Tx DTMF signal with TXLPF and pre-emphasis
Rx DTMF sidetone
Time delay to mute from RX MUTE or TX MUTE
transition
V
IN
= V
IL
to V
IH
V
IN
= V
IH
to V
IL
–0.8
0.5
0.5
5kΩ load (25
°
C)
f = 3kHz
C
L
= 15pF
f = 3kHz
1.2
1.0
0.45
5.2
PARAMETER
TEST CONDITIONS
3kHz
5.9kHz
LIMITS
MIN
8
TYP
9
-52
TBD
100
0.75
40
MAX
9.6
-45
UNIT
dBm0
dBm0
dB
kΩ
V/µs
Ω
V
P-P
V
P-P
V/kHz
dBm0
µs
µs
Table 1. Gain Control Blocks (Bit 0 is Least Significant Bit)
SYMBOL
A1
A2a
A2b
A3
A4
A6
A7
NAMPS
VCO
For A2a, A4 and A7:
For all Gain Blocks:
Bits
4
5
2
4
4
4
4
1
1
MSB sets the sign of the gain
MSB = 0 for gain
MSB = 1 for attenuation
All bits set to 0 = 0dB gain
All bits set to 1 = maximum gain or attenuation
a. A1 compensates for microphone gain variations in the transmit
path.
b. A2a compensates for transmitter dynamic range variations due to
manufacturing tolerances of the SA5753 and SA5752 compandor
companion device. To meet AMPS requirements, the dynamic
range between the zero crossing signal level of the compandor
and the peak signal allowed by the deviation limiter is adjusted to
12.34dB.
c. A2b allows coarse attenuation to be inserted in the transmit path
to eliminate positive feedback effects in hands-free speaker
applications. First step is 12dB followed by two steps of 6dB.
d. A3 sets the gain between the DATA
IN
pin (Pin 19) and the TX
OUT
pin (Pin 20) and should be adjusted after A2a and A4 have been
previously optimized. The SA5753 will interface directly with the
UMA1000T data processor (which produces a 2Vpk data signal).
For NAMPS applications an additional 10 to 14dB resistive divider
must be added at the DATA
IN
pin (Pin 19) for a 2V data signal.
TYPICAL STEP (dB)
–0.8
±0.25
–6, (–12 on first)
–1.0
±0.5
–2.0
±0.5
TYPICAL GAIN (dB)
MIN
–12.0
–3.75
–24.0
–17.0
–3.5
–30.0
–3.5
+1.9 in A2b
–7.6 in A4
+6.0 in A4
MAX
0
+3.75
0
–2.0
+3.5
0
+3.5
FUNCTIONAL DESCRIPTION
The SA5753 is an audio signal processor designed to meet the
requirements of compact low voltage radio telephone equipment. It
includes transmit and receive bandpass filters for voiceband
(300-3000Hz) with pre-emphasis and de-emphasis respectively, a
transmit peak deviation limiter, voice channel mute switches and a
data path which can be summed into the transmit channel. An I
2
C
interface is provided for software programmability of a DTMF
generator, mute polarity, selection of different power down and
operating modes and control of the gain in both the transmit and
receive channels.
Software programmable gain control allows the device to be
automatically optimized during equipment production and offers
flexibility during normal operation.
Gain Blocks
The programmable gain blocks are shown in Table 1 and Figure 2.
The purpose for each block is as follows:
1997 Nov 07
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