INTEGRATED CIRCUITS
SA8026
2.5GHz low voltage fractional-N
dual frequency synthesizer
Product specification
Supersedes data of 1999 Apr 16
1999 Nov 04
Philips
Semiconductors
Philips Semiconductors
Product specification
2.5GHz low voltage fractional-N dual frequency
synthesizer
SA8026
GENERAL DESCRIPTION
The SA8026 BICMOS device integrates programmable dividers,
charge pumps and a phase comparator to implement a
phase-locked loop. The device is designed to operate from 3 NiCd
cells, in pocket phones, with low current and nominal 3 V supplies.
The synthesizer operates at VCO input frequencies up to 2.5 GHz.
The synthesizer has fully programmable main, auxiliary and
reference dividers. All divider ratios are supplied via a 3-wire serial
programming bus.
Separate power and ground pins are provided to the analog and
digital circuits. The ground leads should be externally short-circuited
to prevent large currents flowing across the die and thus causing
damage. V
DDCP
must be greater than or equal to V
DD
.
The charge pump current (gain) is set by an external resistance at
R
SET
pin
.
Passive loop filters could be used; the charge pump
operates within a wide voltage compliance range to provide a wider
tuning range.
LOCK
TEST
V
DD
GND
RFin+
RFin–
GND
CP
PHP
PHI
1
2
3
4
5
6
7
8
9
20 PON
19 STROBE
18 DATA
17 CLOCK
16 REFin+
15 REFin–
14 R
SET
13 V
DDCP
12 AUXin
11 PHA
GND
CP
10
SR01649
Figure 1. Pin Configuration
FEATURES
APPLICATIONS
•
Low phase noise
•
Low power
•
Fully programmable main and auxiliary dividers
•
Normal & Integral charge pumps outputs
•
Fast Locking Adaptive mode design
•
Internal fractional spurious compensation
•
Hardware and software power down
•
Split supply for V
DD
and V
DDCP
QUICK REFERENCE DATA
SYMBOL
V
DD
V
DDCP
I
DDCP
+I
DD
I
DDCP
+I
DD
f
VCO
f
AUX
f
REF
f
PC
T
amb
PARAMETER
Supply voltage
Analog supply voltage
Total supply current
Total supply current in power-down mode
Input frequency
Input frequency
Crystal reference input frequency
Maximum phase comparator frequency
Operating ambient temperature
•
350 to 2500 MHz wireless equipment
•
Cellular phones (all standards)
•
WLAN
•
Portable battery-powered radio equipment.
CONDITIONS
MIN.
2.7
TYP.
–
–
10
1
–
–
–
MAX.
5.5
5.5
12
–
2500
550
40
4
UNIT
V
V
mA
µA
MHz
MHz
MHz
MHz
°C
V
DDCP
w
V
DD
Main and Aux. on
2.7
–
–
350
20
5
–
–40
–
+85
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SA8026DH
TSSOP20
DESCRIPTION
Plastic thin shrink small outline package; 20 leads; body width 4.4 mm
VERSION
SOT360–1
1999 Nov 04
2
853–2141 22633
Philips Semiconductors
Product specification
2.5GHz low voltage fractional-N dual frequency
synthesizer
SA8026
V
DD
3
17
CLOCK
DATA
18
2–BIT SHIFT
REGISTER
22–BIT SHIFT
REGISTER
PUMP
CURRENT
SETTING
PUMP
BIAS
V
DDCP
13
STROBE
19
ADDRESS DECODER
CONTROL
LATCH
14
R
SET
LOAD SIGNALS
LATCH
5
RFin+
RFin–
6
MAIN DIVIDER
PHASE
DETECTOR
8
PHP
COMP
AMP
SM
LATCH
16
REFin+
REFin–
15
SA
1
LOCK
REFERENCE
DIVIDER
2 2 22
9
PHI
LATCH
AUXin
12
AUX DIVIDER
AMP
TEST
2
4
GND
PHASE
DETECTOR
11
PHA
20
7, 10
GND
CP
PON
SR01496
Figure 2. Block Diagram
PINNING
SYMBOL
LOCK
TEST
V
DD
GND
RFin+
RFin–
GND
CP
PHP
PHI
GND
CP
PIN
1
2
3
4
5
6
7
8
9
10
DESCRIPTION
Lock detect output
Test (should be either grounded or
connected to V
DD
)
Digital supply
Digital ground
RF input to main divider
RF input to main divider
Charge pump ground
Main normal charge pump
Main integral charge pump
Charge pump ground
SYMBOL
PHA
AUXin
V
DDCP
R
SET
REFin–
REFin+
CLOCK
DATA
STROBE
PON
PIN
11
12
13
14
15
16
17
18
19
20
DESCRIPTION
Auxiliary charge pump output
Input to auxiliary divider
Charge pump supply voltage
External resistor from this pin to ground
sets the charge pump current
Reference input
Reference input
Programming bus clock input
Programming bus data input
Programming bus enable input
Power down control
1999 Nov 04
3
Philips Semiconductors
Product specification
2.5GHz low voltage fractional-N dual frequency
synthesizer
SA8026
Limiting values
SYMBOL
V
DD
V
DDCP
∆V
DDCP
–V
DD
V
n
V
n
∆V
GND
T
stg
T
amb
T
j
Digital supply voltage
Analog supply voltage
Difference in voltage between V
DDCP and
V
DD
(V
DDCP
≥
V
DD
)
Voltage at pins 1, 2, 5, 6, 12, 15 to 20
Voltage at pin 8, 9, 11
Difference in voltage between GND
CP
and GND (these pins should be
connected together)
Storage temperature
Operating ambient temperature
Maximum junction temperature
PARAMETER
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–55
–40
MIN.
+5.5
+5.5
+2.8
V
DD
+ 0.3
V
DDCP
+ 0.3
+0.3
+125
+85
150
MAX.
V
V
V
V
V
V
_C
_C
_C
UNIT
Handling
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal
precautions appropriate to handling MOS devices.
Thermal characteristics
SYMBOL
R
th j–a
PARAMETER
Thermal resistance from junction to ambient in free air
VALUE
135
UNIT
K/W
1999 Nov 04
4
Philips Semiconductors
Product specification
2.5GHz low voltage fractional-N dual frequency
synthesizer
SA8026
CHARACTERISTICS
V
DDCP
= V
DD
= +3.0V, T
amb
= +25°C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply; pins 3, 13
V
DD
V
DDCP
I
DDTotal
I
Standby
Digital supply voltage
Analog supply voltage
Synthesizer operational total supply current
Total supply current in power-down mode
V
DDCP
w
V
DD
V
DD
= +3.0V
(with main and aux on)
logic levels 0 or V
DD
2.7
2.7
–
–
–
–
10
1
5.5
5.5
12
–
V
V
mA
µΑ
RFin main divider input; pins 5, 6
f
VCO
V
RFin(rms)
VCO input frequency
AC-coupled input signal level
R
in
(external) = R
s
= 50Ω;
single-ended drive;
max. limit is indicative
@ 500 to 2500 MHz
f
VCO
= 2.4 GHz
f
VCO
= 2.4 GHz
350
–18
–
–
2500
0
MHz
dBm
Z
IRFin
C
IRFin
N
main
f
PCmax
Input impedance (real part)
Typical pin input capacitance
Main divider ratio
Maximum loop comparison frequency
–
–
512
300
1
–
–
–
–
65535
4
Ω
pF
indicative, not tested
–
MHz
AUX reference divider input; pin 12
f
AUXin
V
AUXin
Z
AUXin
C
AUXin
N
AUX
Input frequency range
AC-coupled
AC coupled input signal level
Input impedance (real part)
Typical pin input capacitance
Auxiliary division ratio
R
in
(external) = R
S
= 50Ω;
(
)
max. limit is indicative
f
VCO
= 500 MHz
f
VCO
= 500 MHz
20
–18
80
–
–
128
–
–
–
3.9
0.5
–
550
0
632
–
–
16383
MHz
dBm
mV
PP
kΩ
pF
Reference divider input; pins 15, 16
f
REFin
V
RFin
Z
REFin
C
REFin
R
REF
Input frequency range from TCXO
AC-coupled input signal level
Input impedance (real part)
Typical pin input capacitance
Reference division ratio
single-ended drive;
max. limit is indicative
f
REF
= 20 MHz
f
REF
= 20 MHz
SA = SM = ”000”
5
360
–
–
4
–
–
10
1
–
40
1300
–
–
1023
MHz
mV
PP
kΩ
pF
Charge pump current setting resistor input; pin 14
R
SET
V
SET
External resistor from pin to ground
Regulated voltage at pin
R
SET
= 7.5 kΩ
6
–
7.5
1.25
15
–
kΩ
V
Charge pump outputs (including fractional compensation pump); pins 8, 9, 11; R
SET
= 7.5 kΩ, FC = 80
I
CP
I
MATCH
I
ZOUT
I
LPH
V
PH
Charge pump current ratio to I
SET1
Sink-to-source current matching
Output current variation versus V
PH2
Charge pump off leakage current
Charge pump voltage compliance
Current gain = I
PH
/I
SET
V
PH
= 1/2 V
DDCP
V
PH
in compliance range
V
PH
= 1/2 V
DDCP
–15
–10
–10
–10
0.7
–
+15
+10
+10
+10
V
DDCP
–0.8
%
%
%
nA
V
1999 Nov 04
5
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