Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
GENERAL DESCRIPTION
The SA8027 BICMOS device integrates programmable dividers,
charge pumps and phase comparators to implement phase-locked
loops. The device is designed to operate from 3 NiCd cells, in
pocket phones, with low current and nominal 3 V supplies.
The synthesizer operates at VCO input frequencies up to 2.5 GHz.
The synthesizer has fully programmable main, auxiliary and
reference dividers. All divider ratios are supplied via a 3-wire serial
programming bus. The main divider is a fractional-N divider with
programmable integer ratios from 512 to 65535.
Separate power and ground pins are provided to the charge pumps
and digital circuits. The ground pins should be externally connected
to prevent large currents from flowing across the die and causing
damage. V
DDCP
must be equal to or greater than V
DD
.
The charge pump current (gain) is fully programmable, while I
SET
is
set by an external resistance at the R
SET
pin (refer to section 1.5,
Main Output Charge Pumps and Fractional Compensation
Currents)
.
The phase/frequency detector charge pump outputs allow
for implementing a passive loop filter.
LOCK
TEST
V
DD
GND
RFin+
RFin–
GND
CP
PHP
PHI
1
2
3
4
5
6
7
8
9
20 PON
19 STROBE
18 DATA
17 CLOCK
16 REFin+
15 REFin–
14 R
SET
13 V
DDCP
12 AUXin
11 PHA
GND
CP
10
SR01649
Figure 1. TSSOP20 Pin Configuration
STROBE
20
LOCK
TEST
PHP
PHI
PHA
APPLICATIONS
•
500 to 2500 MHz wireless equipment
•
Cellular phones (all standards)
•
WLAN
•
Portable battery-powered radio equipment.
QUICK REFERENCE DATA
SYMBOL
V
DD
V
DDCP
I
DDCP
+I
DD
I
DDCP
+I
DD
f
VCO
f
AUX
f
REF
f
PC
T
amb
PARAMETER
Supply voltage
Analog supply voltage
Supply current
Total supply current in power-down mode
Input frequency
Input frequency
Crystal reference input frequency
Maximum phase comparator frequency
Operating ambient temperature
V
DDCP
w
V
DD
Main and Aux. on
CONDITIONS
GND
CP
AUXin
N/C
FEATURES
•
Low phase noise
•
Low power
•
Fully programmable main and auxiliary dividers
•
Programmable Normal & Integral charge pumps outputs
•
Fast Locking Adaptive mode design
•
Internal fractional spurious compensation
•
Hardware and software power down
•
Split supply for V
DD
and V
DDCP
•
Loop filter bandwidth programmability
V
DDPre
GND
GND
Pre
RFin+
RFin–
GND
CP
1
2
3
4
5
6
7
24
V
DD
23
22
21
19
18
17
CLOCK
REFin+
REFin–
R
SET
V
DDCP
N/C
TOP VIEW
16
15
14
8
9
10
11
12
13
DATA
PON
SR02176
Figure 2. HBCC24 Pin configuration
MIN.
2.7
2.7
–
–
500
100
5
–
–40
TYP.
–
–
7.7
1
–
–
–
–
MAX.
3.6
3.6
–
–
2500
550
40
4
+85
UNIT
V
V
mA
µA
MHz
MHz
MHz
MHz
°C
ORDERING INFORMATION
TYPE NUMBER
SA8027DH
SA8027W
PACKAGE
NAME
TSSOP20
HBCC24
DESCRIPTION
Plastic thin shrink small outline package; 20 leads; body width 4.4 mm
Plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm (Note 1)
VERSION
SOT360-1
SOT564-1
NOTE:
1. The SA8027W will be released for production Q2, 2001.
2001 Aug 21
2
853–2244 26947
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
V
DD
3
17
CLOCK
DATA
18
2–BIT SHIFT
REGISTER
22–BIT SHIFT
REGISTER
PUMP
CURRENT
SETTING
PUMP
BIAS
V
DDCP
13
STROBE
19
ADDRESS DECODER
CONTROL
LATCH
14
R
SET
LOAD SIGNALS
LATCH
5
RF/MAINin+
RF/MAINin–
6
MAIN DIVIDER
FRAC
COMP
PHASE
DETECTOR
8
PHP
AMP
SM
LATCH
16
REFin+
REFin–
15
SA
LOCK
SELECT
1
LOCK
REFERENCE
DIVIDER
2 2 22
9
PHI
LATCH
IF/AUXin
12
AUX DIVIDER
AMP
TEST
2
4
GND
PHASE
DETECTOR
11
PHA
20
7, 10
GND
CP
PON
SR02357
Figure 3. Block Diagram (TSSOP20)
TSSOP20 PIN DESCRIPTION
SYMBOL
LOCK
TEST
V
DD
GND
RFin+
RFin–
GND
CP
PHP
PHI
GND
CP
PIN
1
2
3
4
5
6
7
8
9
10
DESCRIPTION
Lock detect output
Test (should be either grounded or
connected to V
DD
)
Digital supply
Digital ground
RF input to main divider
RF input to main divider
Charge pump ground
Main normal charge pump
Main integral charge pump
Charge pump ground
SYMBOL
PHA
AUXin
V
DDCP
R
SET
REFin–
REFin+
CLOCK
DATA
STROBE
PON
PIN
11
12
13
14
15
16
17
18
19
20
DESCRIPTION
Auxiliary charge pump output
Input to auxiliary divider
Charge pump supply voltage
External resistor from this pin to ground
sets the charge pump current
Reference input
Reference input
Programming bus clock input
Programming bus data input
Programming bus enable input
Power down control
2001 Aug 21
3
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
V
DD
24
18
CLOCK
DATA
19
2–BIT SHIFT
REGISTER
22–BIT SHIFT
REGISTER
PUMP
CURRENT
SETTING
PUMP
BIAS
V
DDpre
1
V
DDCP
14
STROBE
20
ADDRESS DECODER
CONTROL
LATCH
15
R
SET
LOAD SIGNALS
LATCH
4
RF/MAINin+
RF/MAINin–
5
MAIN DIVIDER
FRAC
COMP
PHASE
DETECTOR
7
PHP
AMP
SM
LATCH
17
REFin+
REFin–
16
SA
LOCK
SELECT
22
LOCK
REFERENCE
DIVIDER
2 2 22
8
PHI
LATCH
IF/AUXin
11
AUX DIVIDER
AMP
TEST
23
2
GND
3
GND
pre
PHASE
DETECTOR
10
PHA
21
6, 9
GND
CP
PON
SR02358
Figure 4. Block Diagram (HBCC24)
HBCC24 PIN DESCRIPTION
SYMBOL
V
DDPre
GND
GND
Pre
RFin+
RFin–
GND
CP
PHP
PHI
GND
CP
PHA
AUXin
N/C
N/C
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
DESCRIPTION
Prescaler supply voltage
Digital ground
Prescaler ground
RF input to main divider
RF input to main divider
Charge pump ground
Main normal charge pump
Main integral charge pump
Charge pump ground
Auxiliary charge pump output
Input to auxiliary divider
Not connected
Not connected
REFin–
REFin+
CLOCK
DATA
STROBE
PON
LOCK
TEST
V
DD
16
17
18
19
20
21
22
23
24
SYMBOL
V
DDCP
R
SET
PIN
14
15
DESCRIPTION
Charge pump supply voltage
External resistor from this pin to ground
sets the charge pump current
Reference input
Reference input
Programming bus clock input
Programming bus data input
Programming bus enable input
Power down control
Lock detect output
Test (should be either grounded or
connected to V
DD
)
Digital supply
2001 Aug 21
4
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
Limiting values
SYMBOL
V
DD
V
DDCP
∆(V
DDCP
–V
DD
)
Vi
n
∆V
GND
T
stg
T
amb
T
j
Digital supply voltage
Analog supply voltage
Difference in voltage between V
DDCP and
V
DD
(V
DDCP
≥
V
DD
)
All input pins
Difference in voltage between GND
CP
and GND (these pins should be
connected together)
Storage temperature
Operating ambient temperature
Maximum junction temperature
PARAMETER
–0.3
–0.3
–0.3
–0.3
–0.3
–55
–40
MIN.
+3.6
+3.6
+0.9
V
DD
+ 0.3
+0.3
+125
+85
150
MAX.
V
V
V
V
V
°C
°C
°C
UNIT
Thermal characteristics
SYMBOL
R
th j–a
PARAMETER
Thermal resistance from junction to ambient in free air
VALUE
135
UNIT
K/W
2001 Aug 21
5
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