INTEGRATED CIRCUITS
DATA SHEET
SAA2013
Adaptive allocation and scaling for
PASC coding in DCC systems
Preliminary specification
File under Integrated Circuits, IC01
May 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
FEATURES
•
Wide operating voltage range: 2.7 to 5.5 V
•
Low power consumption: 13 mW; 3.0 V
•
Low power decode mode: 1 mW; 5.0 V
•
Sleep mode for low power and low Electromagnetic
Interference (EMI)
•
Sophisticated allocation algorithm
•
Optimum sound quality
•
Three-wire L3 bus microcontroller interface
•
Stereo or 2-channel mono recording
•
Small surface mounted package (QFP; SOT307).
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
SAA2013H
Note
44
PIN POSITION
QFP
(1)
MATERIAL
plastic
GENERAL DESCRIPTION
SAA2013
The SAA2013 performs the adaptive allocation and
scaling function in the Precision Adaptive Sub-band
Coding (PASC) system. It is not required in playback only
applications, and is only used during recording. To
complete the PASC processor, a SAA2003 stereo filter
and codec is required.
CODE
SOT307-2
1. When using reflow soldering it is recommended that the Dry Packing instructions in the
“Quality Reference
Pocketbook”
are followed. The pocketbook can be ordered using the code 9398 510 34011.
May 1994
2
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
BLOCK DIAGRAM
SAA2013
handbook, full pagewidth
VDD1 VDD2
14
24
VDD3
40
FS256
39
FRESET
FDAI
FDIR
FSYNC
37
36
35
34
L3MODEM
L3CLKM
L3DATAM
3
4
5
MICROCONTROLLER
BUS
CONTROL
AND
SYNC
COMPENSATION
DELAY
32
31
30
26
23
33
FDCL
FDWS
SLEEP
CLK24
RESET
FDAO
SFC
BUS
ALLOCATION AND SCALE FACTOR
COMPUTATION
SAA2013
9
10
11
L3MODEC
L3CLKC
L3DATAC
6
25
44
20
21
22
RESOL1
MGB355
VSS1
VSS2
VSS3
NODONE RESOL0
Fig.1 Block diagram.
May 1994
3
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
PINNING
SYMBOL
TEST10
TEST11
L3MODEM
L3CLKM
L3DATAM
V
SS1
TEST12
TEST13
L3MODEC
L3CLKC
L3DATAC
TEST1
TEST2
V
DD1
TEST3
TEST4
TEST5
TEST6
TEST7
NODONE
RESOL0
RESOL1
RESET
V
DD2
V
SS2
CLK24
LOWPWR
POR
TEST8
SLEEP
FDWS
FDCL
FDAO
FDAI
FSYNC
FRESET
FDIR
TEST9
FS256
V
DD3
May 1994
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
test input; connect to V
SS
test input; connect to V
SS
microcontroller interface mode input
microcontroller interface clock input
microcontroller interface data 3-state input/output
supply ground
test output; do not connect
test output; do not connect
codec interface mode output
codec interface clock output
codec interface data 3-state input/output
test output; do not connect
test output; do not connect
supply voltage
test mode input; connect to V
DD
test mode input; connect to V
DD
test input; connect to V
SS
test input; connect to V
SS
test input; connect to V
SS
nodone state selection input; connect to V
DD
resolution selection 0 input
resolution selection 1 input
reset input; active HIGH
supply voltage
supply ground
24.576 MHz clock input
low power decode select input
power on reset input
test input; connect to V
SS
sleep mode select input
filtered data word select
filtered data clock
filtered data output
filtered data input
sub-band synchronization on filtered I
2
S bus
reset signal input from SAA2003
filtered data direction input
test input; connect to V
SS
system clock input; 256
×
sample frequency (f
s
)
supply voltage
4
DESCRIPTION
SAA2013
TYPE
I
I
I
I
I/O
−
O
O
O
O
I/O
O
O
−
I
I
I
I
I
I
I
I
I
−
−
I
I
I
I
I
I
I
O
I
I
I
I
I
I
−
Philips Semiconductors
Preliminary specification
Adaptive allocation and scaling for PASC
coding in DCC systems
SYMBOL
n.c.
n.c.
n.c.
V
SS3
PIN
41
42
43
44
not connected
not connected
not connected
supply ground
DESCRIPTION
SAA2013
TYPE
−
−
−
−
36 FRESET
35 FSYNC
38 TEST9
39 FS256
40 VDD3
44 VSS3
37 FDIR
43 n.c.
TEST10
TEST11
L3MODEM
L3CLKM
L3DATAM
VSS1
TEST12
TEST13
L3MODEC
42 n.c.
41 n.c.
handbook, full pagewidth
34 FDAI
1
2
3
4
5
6
7
8
9
33 FDAO
32 FDCL
31 FDWS
30 SLEEP
29 TEST8
SAA2013
28 POR
27 LOWPWR
26 CLK24
25 VSS2
24 VDD2
23 RESET
L3CLKC 10
L3DATAC 11
NODONE 20
RESOL0 21
RESOL1 22
TEST1 12
TEST2 13
VDD1 14
TEST3 15
TEST4 16
TEST5 17
TEST6 18
TEST7 19
MGB356
Fig.2 Pin configuration.
May 1994
5
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