INTEGRATED CIRCUITS
DATA SHEET
SAA2023
Drive processor for DCC systems
Preliminary specification
File under Integrated Circuits, IC01
May 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
FEATURES
•
Operating supply voltage: 4.5 to 5.5 V
•
Low power dissipation: 260 mW at 5.0 V
•
Single chip digital equalizer, tape formatting and error
correction
•
8-bit flash analog-to-digital converter (ADC) for low
symbol error rate
•
Two switchable Infinite Impulse-Response (IIR) filter
sections
•
10-tap Finite Impulse-Response (FIR) filter per main
data channel, with 8 bit coefficients, identical for all main
channels
•
10-tap FIR filter for the AUX channel
•
Analog and digital eye outputs
•
Interrupt line triggered by internal auxiliary envelope
processing e.g. label, counter, and others
•
Robust programmable digital PLL clock extraction unit
•
Low power SLEEP mode
•
Slew rate limited Electromagnetic Compatibility (EMC)
friendly output
•
Digital Compact Cassette (DCC) optimized error
correction
•
Programmable symbol synchronization strategy for tape
input data
•
Microcontroller control of capstan servo possible during
playback and recording
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
PINS
SAA2023H
SAA2023GP
Note
80
80
PIN POSITION
TQFP80
(1)
QFP80
(1)
MATERIAL
plastic
plastic
SAA2023
•
Frequency and phase regulation of capstan servo
during playback
•
Choice of Dynamic Random Access Memory (DRAM)
and Static Random Access Memory (SRAM) types for
system Random Access Memory (RAM)
•
Scratch pad RAM for microcontroller in system RAM
•
Integrated interface for Precision Adaptive Sub-band
Coding (PASC) data bus
•
Three wire microcontroller ‘L3’ interface
•
Protection against invalid auxiliary data
•
Seamless joins between recordings.
GENERAL DESCRIPTION
The SAA2023 performs the drive processor function in the
DCC system. This function is built up of digital equalizer,
error correction and tape formatting functions. The digital
equalizer is intended for use with DCC read amplifiers
TDA1318 or TDA1380. The tape formatting and error
correction circuit is intended for use with PASC ICs
SAA2003 and SAA2013, and write amplifiers TDA1319 or
TDA1381.
CODE
SOT315-1
SOT318-2
1. When using reflow soldering it is recommended that the Dry Packing instructions in the
“Quality Reference
Pocketbook”
are followed. The pocketbook can be ordered using the code 9398 510 34011.
May 1994
2
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
BLOCK DIAGRAM
SAA2023
handbook, full pagewidth
SAA2023
DIGITAL-
TO-ANALOG
CONVERTER
ANAEYE
RDSYNC
RDMUX
BIAS
Vref(p)
Vref(n)
PHASE
LOCKED
LOOP
ZERO
CROSSING
FIR
(1)
IIR
(2)
ANALOG
TO-DIGITAL
CONVERTER
TAPE
INPUT
BUFFER
SBDIR
SBMCLK
SBEF
SBDA
SBCL
SBWS
AUXILIARY
ENVELOPE
DETECTION
EQUALIZER
MODULE
SUB-BAND
I
2
S
INTERFACE
INTERNAL DATA BUS
TAPE
OUTPUT
BUFFER
TCLOCK
WDATA
ERROR
CORRECTOR
RAM
INTERFACE
CONTROL
INTERFACE
SPEED
URDA
RESET
SLEEP
L3REF
L3DATA
8 11
6
MGB378
A11 to A16
L3MODE
PINO1
PINO2
OEN
D0 to D7
L3INT
WEN
A0 to A10
(1) FIR = Finite Impulse-Response.
(2) IIR = Infinite Impulse-Response.
Fig.1 Block diagram.
May 1994
3
L3CLK
PINI
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
PINNING
PIN
SYMBOL
QFP80
SBWS
SBCL
SBDA
SBDIR
SBMCLK
URDA
L3MODE
L3CLK
L3DATA
L3INT
V
DD1
V
SS1
L3REF
RESET
SLEEP
CLK24
AZCHK
MCLK
TEST3
ERCOSTAT
OEN
A10/RAS
V
DD2
V
SS2
D7
D6
D5
D4
D3
D2
D1
V
DD7
V
SS7
D0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
TQFP80
79
80
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
word select for sub-band PASC interface
bit clock for sub-band PASC interface
data line for sub-band PASC interface
direction line for sub-band PASC interface
master clock for sub-band PASC interface
unreliable data
mode line for L3 interface
bit clock line for L3 interface
serial data line for L3 interface
L3 interrupt output
digital supply voltage
digital ground
L3 bus timing reference
reset SAA2023
sleep mode selection of SAA2023
24.576 MHz clock input
channel 0 and channel 7 azimuth monitor
6.144 MHz clock output
TEST3 output; do not connect
ERCO status, for symbol error rate measurements
output enable for RAM
address SRAM; RAS DRAM
digital supply voltage
digital ground
data SRAM
data SRAM
data SRAM
data SRAM
data SRAM; data DRAM
data SRAM; data DRAM
data SRAM; data DRAM
digital supply voltage for RAM
digital ground for RAM
data SRAM; data DRAM
address SRAM; address DRAM
address SRAM; address DRAM
address SRAM; address DRAM
address SRAM; address DRAM
DESCRIPTION
SAA2023
TYPE
(1)
I/O (1 mA)
I/O (1 mA)
I/O (1 mA)
O (1 mA)
I
O (1 mA)
I
I
I/O (2 mA)
O (1 mA)
S
S
O (1 mA)
I
I
I
O (1 mA)
O (1 mA)
O (1 mA)
O (1 mA)
O (2 mA)
O (2 mA)
S
S
I/O (4 mA)
I/O (4 mA)
I/O (4 mA)
I/O (4 mA)
I/O (4 mA)
I/O (4 mA)
I/O (4 mA)
S
S
I/O (4 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
May 1994
4
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA2023
PIN
SYMBOL
QFP80
A4
V
SS3
V
DD3
A5
A6
A7
A12/PINO5
A14/PINO1
A16/PINO3
A15/PINO4
WEN
A13/PINO2
A8
V
DD4
V
SS4
A9/CAS
A11
SPEED
PINO2
WDATA
TCLOCK
V
SS5
V
DD5
TEST2
RDMUX
V
ref(p)
V
ref(n)
SUBSTR
BIAS
V
SSA
V
DDA
ANAEYE
RDSYNC
V
DD6
V
SS6
CHTST1
CHTST2
TEST0
TEST1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
TQFP80
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
address SRAM; address DRAM
digital ground
digital supply voltage
address SRAM; address DRAM
address SRAM; address DRAM
address SRAM; address DRAM
address SRAM; Port expander output 5
address SRAM; Port expander output 1
address SRAM; Port expander output 3
address SRAM; Port expander output 4
write enable for RAM
address SRAM; Port expander output 2
address SRAM; address DRAM
digital supply voltage
digital ground
address SRAM; CAS for DRAM
address SRAM
Port expander output 2
serial output to write amplifier
3.072 MHz clock output for tape I/O
digital ground
digital supply voltage
TEST mode select; do not connect
analog multiplexed input from read amplifier
ADC positive reference voltage
ADC negative reference voltage
substrate connection
bias current for ADC
analog ground
analog supply voltage
analog eye pattern output
synchronization output for read amplifier
digital supply voltage
digital ground
channel test pin 1
channel test pin 2
TEST mode select; do not connect
TEST mode select; do not connect
DESCRIPTION
TYPE
(1)
O (2 mA)
S
S
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
O (2 mA)
S
S
O (2 mA)
O (2 mA)
O
t
(1 mA)
O (1 mA)
O (1 mA)
S
S
I
pd
I
A
I
A
I
A
I
A
I
A
S
S
O
A
O (1 mA)
S
S
O (1 mA)
O (1 mA)
I
pd
I
pd
Pulse Width Modulation (PWM) capstan control output for deck O
t
(1 mA)
May 1994
5
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