INTEGRATED CIRCUITS
DATA SHEET
SAA2501
Digital Audio Broadcast (DAB)
decoder
Preliminary specification
File under Integrated Circuits, IC01
January 1995
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
CONTENTS
FEATURES
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.17.1
7.17.2
7.17.3
7.17.4
7.18
7.19
7.20
7.20.1
7.20.2
7.20.3
7.20.4
7.20.5
7.20.6
7.20.6.1
7.20.7
7.20.8
7.20.9
7.20.10
7.20.11
7.20.12
APPLICATION
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Coding system
Basic functionality
SAA2501 clocks
Crystal oscillator
Clock frequencies when using the slave input
Clock frequencies when using the master input
Target applications; applying the SAA2501 with
2 ISO/MPEG sources
Buffered clock outputs
Functionality issues
Synchronization to input data bitstreams
Master input bit rate selection
Sample rate selection
Handling of errors in the coded input data
sub-band filter signals
Baseband audio processing
Decoding control signals
Coded data interfaces
The coded data master input interface
The coded data slave input interface
Slave input transfer speed of first frame
Slave input transfer speed of subsequent
frames
The sub-band filter interface
The baseband output interface
The L3 control interface
L3 signals
L3 transfer types
L3 interface initialization at an SAA2501 device
reset
L3 interface control
SAA2501 status
Data items
General data items
SAA2501 settings item
Input data frame header items
Error report item
Audio service synchronized data item
Ancillary Data/XPAD item
APU coefficients item
7.20.13
7.20.14
8
8.1
8.1.1
8.1.1.1
8.1.1.2
8.1.1.3
8.1.1.4
8.1.2
8.1.3
8.1.3.1
8.1.3.2
8.1.4
8.1.5
8.1.5.1
8.1.5.2
8.1.5.3
8.2
8.2.1
8.2.2
9
10
11
12
13
14
14.1
14.1.1
14.1.2
14.1.3
15
16
SAA2501
Speed limitations of the L3 interface
Default item data values after reset
APPENDIX
Preliminary specification 3-line ‘L3’ interface
Introduction
Addressing mode
Special function operational address
Data mode
Halt mode
Device interface reset
Extended addressing
Operational address declaration
Operational address invalidation
Example of a data transfer
Timing requirements
Addressing mode
Data mode
Halt mode
SAA2501 L3 protocol enhancement options
Testing L3RDY by polling L3DATA
Options to increase the timing accuracy of the
APU coefficient writing
LIMITING VALUES
DC CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Plastic quad flat-packs
By wave
By solder paste reflow
Repairing soldered joints (by hand-held
soldering iron or pulse-heated solder tool)
DEFINITIONS
LIFE SUPPORT APPLICATIONS
January 1995
2
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
1
FEATURES
2
APPLICATION
SAA2501
•
Advanced error protection
•
Integrated audio post processing for control of signal
level and inter-channel crosstalk
•
Demultiplexing of Program Associated Data (PAD) in
the input bitstream
•
Automatic digital de-emphasis of the decoded
audio signal
•
Separate master and slave inputs
•
Automatic sample frequency and bit-rate switching in
master input mode
•
Automatic synchronization of input and output interface
clocks in master input mode
•
Selectable audio output precision; 16, 18, 20 or 22 bit
•
Low power consumption
•
Decoded sub-band signal and error flag outputs for error
concealment.
4
ORDERING INFORMATION
•
Digital Audio Broadcast systems as defined in
“Eureka 147”.
3
GENERAL DESCRIPTION
The SAA2501 audio source decoder supports ISO/IEC
MPEG layers I and II and all DAB specific features as
described in
“Eureka 147 draft specification (EU147)”.
PACKAGE
TYPE NUMBER
NAME
SAA2501H
Note
1. When using IR reflow soldering it is recommended that the Drypack instructions in the
“Quality Reference Handbook”
(order number 9398 510 63011) are followed.
Supply of this
“ISO/IEC 11172-3”
audio standard Layer I or layer II compatible IC does not convey a licence nor imply a
right under any patent, or any Industrial or Intellectual Property Right, to use this IC in any ready-to-use
electronic product.
QFP44
(1)
DESCRIPTION
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10
×
10
×
1.75 mm
VERSION
SOT307-2
January 1995
3
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
5
BLOCK DIAGRAM
SAA2501
FSCLK384
MCLKOUT
FSCLKIN
MCLK24
X22OUT
L3MODE
FSCLKM
MCLKIN
FSCLK
L3DATA
L3CLK
handbook, full pagewidth
5
TDI
TDO
TCK
TMS
TRST
CDS
CDSEF
CDSCL
CDSWA
CDSSY
CDM
CDMEF
CDMCL
CDMWS
41
37
39
40
38
19
20
18
21
22
15
14
16
13
34
8
7
4
44
10
9
3
2
42 43
24 25 23
11 12
URDA
1
X22IN
MCLK
V
DD1
V
DD2
CLOCK
GENERATOR
DECODING
CONTROL
STOP
RESET
SAA2501
DEQUANTI-
ZATION
AND
SCALING
PROCESSOR
SYNTHESYS
SUBBAND
FILTER
BANK
AND
OUTPUT
PROCESSING
INPUT
PROCESSOR
26
SD
36
TC0
35
TC1
17
GND2
28
GND3
6
GND1
27 33 31 32
FDFSY
FDAO
FDEF
FDAI
29
30
MBE112
SCK WS
Fig.1 Functional block diagram.
January 1995
4
Philips Semiconductors
Preliminary specification
Digital Audio Broadcast (DAB) decoder
6
PINNING
SYMBOL
RESET
FSCLK
FSCLKIN
MCLK
V
DD1
GND1
MCLKOUT
MCLKIN
X22OUT
X22IN
STOP
URDA
CDMWS
CDMEF
CDM
CDMCL
GND2
CDSCL
CDS
CDSEF
CDSWA
CDSSY
L3CLK
L3DATA
L3MODE
SD
FDEF
GND3
SCK
WS
FDAO
FDAI
FDFSY
V
DD2
TC1
TC0
TDO
TRST
TCK
January 1995
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
master reset input
sample rate clock output; buffered signal
sample rate clock signal input (see Table 1)
master clock output; buffered signal
supply voltage 1
ground 1
master clock oscillator output
master clock oscillator input or signal input
22.579 MHz clock oscillator output
22.579 MHz clock oscillator input or signal input
stop decoding input
unreliable data input; interrupt decoding
coded data (master input) word select output
coded data (master input) error flag input
ISO/MPEG coded data (master input)
coded data (master input) bit clock output
ground 2
coded data (slave input) bit clock
ISO/MPEG or EU147 (see Table 8) coded data (slave input)
coded data (slave input) error flag
coded data (slave input) burst window signal
coded data (slave input) frame sync
L3 interface bit clock input
L3 interface serial data input/output
L3 interface address/data select input
baseband audio I
2
S data output
filter data error flag output
ground 3
baseband audio data I
2
S clock output
baseband audio data I
2
S word select output
filter data output
filter data input
filter data output frame sync
supply voltage 2
DESCRIPTION
SAA2501
TYPE
I
O
I
O
−
−
O
I
O
I
I
I
O
I
I
O
−
I
I
I
I
I
I
I/O
I
O
O
−
O
O
O
I
O
−
I
I
O
I
I
do not connect; factory test control 1 input, with integrated pull-down resistor
do not connect; factory test control 0 input, with integrated pull-down resistor
boundary scan test data output
boundary scan test reset input; this pin should be connected to ground for
normal operation
boundary scan test clock input
5
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