Philips Semiconductors
Objective specification
MPEG2 audio decoder
FEATURES
•
Single-chip MPEG2 multichannel audio decoder
•
Decodes MPEG high quality audio:
– MPEG1 layer 2 (44.1 kHz)
– MPEG2 multichannel layer 2 (48 kHz)
– Supports pause frames
•
Outputs 2 channels
– Quasi surround down-mixing for Left and Right Dolby
surround channel (Lt and Rt)
– Stereo down-mixing for stereo reproduction
– Stereo signal selection
– Single channel down-mixing
•
Karaoke modes
•
Linear PCM modes:
– Down-sampling from 96 to 48 kHz
– Pass 48 kHz signals
•
Bitstream input interface
I
2
S-bus
(IEC 1937 formatted)
•
IEC 958 output interface (IEC 1937 formatted)
•
IEC 958 output simultaneously available while decoding
MPEG2
•
I
2
C-bus control
•
Output flags for direct control
•
Stand-alone operation possible (self-booting)
•
No external DRAM or SRAM required
•
On-chip PLL for internal clock generation
•
13.5 or 27 MHz master clock
•
100 pins plastic LQFP package
•
5 V power supply.
ORDERING INFORMATION
TYPE
NUMBER
SAA2503HT
PACKAGE
NAME
LQFP100
DESCRIPTION
plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
APPLICATIONS
SAA2503
This IC is mainly intended for use in Digital Versatile Disc
(DVD) players. However it may also be used in any
application that is able to accept an MPEG2 audio
bitstreams such as:
•
Set top boxes
•
Multimedia PCs
•
Digital television
•
Next generation audio equipment.
GENERAL DESCRIPTION
The SAA2503 incorporates all necessary functions, such
as MPEG2 multichannel audio decoding plus
down-mixing, MPEG1 layer 2 decoding, Linear PCM
(LPCM) processing all producing high quality audio.
Together with the serial audio interfaces and the IEC 958
transmitter this allows for the complete audio function of a
DVD player in a single chip.
VERSION
SOT407-1
1997 Jul 02
2
Philips Semiconductors
Objective specification
MPEG2 audio decoder
PINNING
SYMBOL
n.c.
n.c.
GNDA1
n.c.
n.c.
H7/PB7
H6/PB6
GNDH1
HOA2/PB10
V
CCH1
HOA1/PB9
HR/W/PB11
HEN/PB12
V
CCQ1
GNDQ1
HACK/PB14
GNDH2
HOA0/PB8
H5/PB5
V
CCH2
H4/PB4
H3/PB3
GNDH3
H2/PB2
H1/PB1
H0/PB0
HOREQ/PB13
GNDH4
V
CCH3
ADO
ACI
n.c.
n.c.
n.c.
PLOCK
V
CCQ2
GNDQ2
PINIT
GNDP
PCAP
1997 Jul 02
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
−
−
GND
−
−
I/O
I/O
GND
I/O
supply
I/O
I/O
I/O
supply
GND
I/O
GND
I/O
I/O
supply
I/O
I/O
GND
I/O
I/O
I/O
I/O
GND
supply
O
I
−
−
−
O
supply
GND
I
GND
I
not connected
not connected
ground 1 for some sections of internal logic
not connected
not connected
not used
not used
isolated ground 1 for the HI I/O drivers
not used
DESCRIPTION
SAA2503
isolated power supply 1 for some sections of the internal chip logic
not used
not used
not used
isolated power supply 1 for the HI I/O drivers
isolated ground 1 for the internal logic
not used
isolated ground 2 for the HI I/O drivers
not used
not used
isolated power supply 2 for the HI I/O drivers
not used
not used
isolated ground 3 for the HI I/O drivers
not used
not used
not used
not used
isolated ground 4 for the HI I/O drivers
isolated power supply 3 for the HI I/O drivers
digital audio data output
audio clock input
not connected
not connected
not connected
HIGH when PLL is phase locked
isolated power supply 2 for some sections of the internal chip logic
isolated ground 2 for the internal logic
PLL enable/disable control
ground dedicated for the PLL
PLL capacitor input
4
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
SYMBOL
V
CCP
EXTAL
SCL
GNDS1
SDA
RESET
MODA
MODB
MODC
V
CCS1
HA0
HA2
HREQ
GNDS2
SDO2
SDO1
SDO0
V
CCS2
SCKT
WST
SCKR
GNDQ3
V
CCQ3
GNDS3
WSR
SDI1
SDI0
DSO
DSI/OS0
DSCK/OS1
n.c.
n.c.
n.c.
n.c.
DR
SDB
MUTE
GNDD1
BUSY
I2CEN
V
CCD1
1997 Jul 02
PIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
I/O
supply
I
I
GND
I/O
I
I
I
I
supply
I/O
I
I
GND
O
O
O
supply
O
O
I
GND
supply
GND
I
I
I
O
O
O
−
−
−
−
I
I/O
I/O
GND
I/O
I/O
supply
external clock/crystal Input
I
2
C-bus serial clock
DESCRIPTION
supply voltage for the Phase Locked Loop (PLL)
isolated ground 1 for the SHI I/O drivers
I
2
C-bus data and acknowledge
hardware reset for the microcontroller
mode select A
mode select B
mode select C
isolated power supply 1 for the SHI I/O drivers
I
2
C-bus slave address 0
I
2
C-bus slave address 2
host request
isolated ground 2 for the SHI I/O drivers
not used
not used
serial data output 0
isolated power supply 2 for the SHI I/O drivers
transmit serial clock
transmit word select
receive serial clock
ground 3 dedicated for the PLL
isolated power supply 3 for some sections of the internal chip logic
isolated ground 3 for the SHI I/O drivers
receive word select
serial data input 1
not used
not used
not used
not used
not connected
not connected
not connected
not connected
not used
general purpose I/O
general purpose I/O
ground 1 for some sections of internal logic
general purpose I/O
general purpose I/O
isolated power supply 1 for some sections of the internal chip logic
5
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