Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
FEATURES
(With standard microcode loaded)
•
Decoding and display of MPEG1 video streams
(constrained parameters)
•
Decoding of MPEG audio streams (layer II)
•
Decoding, storage (compressed) and display of
high-resolution still pictures of 704
×
576 pixels
•
Requires only 4 Mbits of external 70 ns DRAM
•
Audio transparency mode for CD-DA discs
•
On-screen display capability
•
Play options:
– Play
– Stop
– Pause/continue
– Slow-motion forward
– Scan forward
– Scan backward.
•
Supports auto-pause feature
•
Disc interface: Philips I
2
S, EIAJ, MEC formats and
IEC 958 (EBU) interface
•
Separate error flag input (EFIN) and data valid input
(NDAV)
•
Performs basic block decoder functions:
– serial-to-parallel conversion
– sync detection
– descrambling
– EDC calculation
– error-correction for mode 2 form 1 sectors
– header and sub-header interpretation.
•
I
2
C-bus interface
•
Video output YUV 4 : 2 : 2 format. DMSD bus
compatible
•
Also supports CCIR656 video interface, including line
and field timing codes
•
Audio output: 44.1 kHz. 16, 18 or 20 bits per audio
sample in Philips I
2
S, Sony or MEC formats
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA2510
QFP100
DESCRIPTION
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14
×
20
×
2.7 mm; high stand-off height
2
APPLICATION
•
Dedicated video CD players.
GENERAL DESCRIPTION
SAA2510
•
EBU audio output, fully transparent from input to output
in CD-DA mode and generated in MPEG mode
•
Downloadable microcode for internal controllers
•
Internal video timing generator
•
Requires 40 MHz crystal for system clock generation
•
Requires 27 MHz crystal or external 27 MHz source for
video timing generation
•
Requires 16.9344 MHz (384
×
44.1 kHz) clock locked to
CD drive
•
Internal generation of 90 kHz MPEG clock
•
Capability of sharing external DRAM by 3-stating all
DRAM pins.
MPEG1 audio and video CD (VCD) decoder, intended for
use in low-cost dedicated video CD players. When used
with a 4 Mbit DRAM and a digital video encoder, the
decoder adds the required functionality to a CD decoder to
implement a low-cost video CD player capable of playing
discs coded to version 2.0 of the video CD specification.
The SAA2510 is an I
2
C-bus controlled chip and features
serial data input in four common bus formats. It provides
digital video output in CCIR601 and 656 formats.
A bit-mapped on-screen display is provided and output
video timing can be 525 lines/30 frames per second or
625 lines/25 frames per second. The chip is microcode
programmable for feature enhancement.
VERSION
SOT317-1
1996 May 21
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
PINNING
SYMBOL
UV6
PIN
1
video UV bus output bit 6;
DESCRIPTION
SAA2510
16-bit video output mode: the UV bus outputs alternating U and V chroma samples
at 13.5 Mbytes/s
CCIR656 mode: this bus is not used (inactive)
UV5
UV4
UV3
UV2
UV1
UV0
V
DD5
CSYNC
V
SS5
TLSAND
EBUOUT
DAOUT
WSOUT
V
DD3
CLOUT
V
SS
AUDIOCLK
V
DD5
EBUIN
CLIN
WSIN
DAIN
V
DD3
EFIN
V
SS
RESET
DRAMON
INT
NDAV
ASEL
SDA
V
DD5
SCL
V
SS5
DR15
1996 May 21
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
video UV bus bit 5
video UV bus bit 4
video UV bus bit 3
video UV bus bit 2
video UV bus bit 1
video UV bus bit 0
5 V external pad power supply
composite sync output; 525 lines/60 Hz or 625 lines/50 Hz
0 V external pad power supply
two-level Sandcastle (composite blanking) output; requires external resistor network
to define horizontal/vertical blanking level
IEC 958 digital audio output
I
2
S data; digital audio output
I
2
S word select digital audio output
+3 V internal power supply
I
2
S bit clock output
0 V internal power supply
16.9 MHz audio clock input
5 V internal power supply
EBU (IEC 958) input
I
2
S bit clock input
I
2
S word select input
I
2
S digital data input
+3 V internal power supply
error flag input from I
2
S source
0 V internal power supply
active low reset input
DRAM pin 3-state control input; also 3-states video outputs and some timing signals
active low open drain interrupt request to host microcontroller
data not valid input (data on I
2
S or EBU input not valid)
I
2
C-bus address select pin
I
2
C-bus data pin
5 V external pad power supply
I
2
C-bus clock input
0 V external pad power supply
DRAM data input/output bit 5
5
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