Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG
layer 1 audio compression applications
FEATURES
•
Stereo or 2-channel mono encoding
•
Status may be read continuously
•
Microcontroller interface
•
I
2
S-interfaces
•
Allocation algorithm including optional emphasis
correction (for 44.1 kHz)
•
Reduced power consumption
•
4 V nominal operating voltage capability.
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
SAA2521GP
Note
1. SOT205-1; 1996 August 23.
PACKAGE
PINS
44
PIN POSITION
QFP
MATERIAL
plastic
GENERAL DESCRIPTION
SAA2521
The SAA2521 performs the adaptive allocation and
scaling function for calculating the masking thresholds and
sub-band sample accuracy in MPEG layer 1 applications.
The SAA2521 is intended for use in conjunction with the
stereo filter codec SAA2520.
CODE
SOT205AG
(1)
August 1993
2
Philips Semiconductors
Preliminary specification
Masking threshold processor for MPEG
layer 1 audio compression applications
PINNING
SYMBOL
LTCNT1
LTCNT0
LTENA
LTCLK
LTDATA
V
SS
LTCNT1C
LTCNT0C
LTENC
LTCLKC
LTDATAC
TEST1
TEST2
V
DD
TEST3
TEST4
TEST5
TEST6
TEST7
NODONE
RESOL0
RESOL1
RESET
V
DD
V
SS
CLK24
TEST8
TEST9
TEST10
PWRDWN
SWS
SCL
FDAC
FDAF
FSYNC
FRESET
FDIR
SCALE
FS256
V
DD
August 1993
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DESCRIPTION
mode control 1, microcontroller interface input
mode control 0, microcontroller interface input
enable microcontroller interface input
bit clock microcontroller interface input
data, microcontroller interface (3-state inputs/outputs)
supply ground (0 V)
control 1; microcomputer interface
control 0; microcomputer interface
enable microcontroller interface
bit clock; microcontroller interface
data; microcontroller interface, (3-state inputs/outputs)
test output; do not connect
test output; do not connect
positive supply voltage (+ 5 V)
test mode input; to be connected to V
DD
test mode input; to be connected to V
DD
test input; to be connected to V
SS
test input; to be connected to V
SS
test input; to be connected to V
SS
no done state selection input
resolution selection 0 input
resolution selection 1 input
active HIGH reset input
positive supply voltage (+ 5 V)
supply ground (0 V)
24.576 MHz processing clock input
test input; to be connected to V
SS
test input; to be connected to V
SS
test input; to be connected to V
SS
power-down input
word selection input; (Filtered) - I
2
S-interface
bit clock input; (Filtered) - I
2
S-interface
filtered data (Filtered) - I
2
S-interface (3-state inputs/outputs)
filtered data (Filtered) - I
2
S-interface (3-state inputs/outputs)
sub-band synchronization on (Filtered) - I
2
S-interface, input
reset signal input from SAA2520
direction of the I
2
S-interface; input
scale factor index select (note 1)
system clock input; sample frequency
×
256
positive supply voltage (+ 5 V)
5
SAA2521
TYPE
I
I
I
I
I/O
O
O
O
O
I/O
I
I
I
I
I
I
I
I
I/O
I/O
I
I
I
I
I
嵌入式系统
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