INTEGRATED CIRCUITS
DATA SHEET
SAA3500H
Digital audio broadcast channel
decoder
Preliminary specification
File under Integrated Circuits, IC01
2000 Jun 14
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
CONTENTS
1
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.7.1
9.7.2
9.7.3
10
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
INTERFACE DESCRIPTION
Input interface
Memory interface
Parallel output interface
Serial output interface
Simple full capacity output
RDI output
Microcontroller interface
I
2
C-bus mode
L3-bus mode
Microcontroller interface registers
LIMITING VALUES
16.2
16.3
16.4
16.5
17
18
19
20
11
12
13
14
14.1
14.2
14.3
15
16
16.1
SAA3500H
THERMAL CHARACTERISTICS
DC CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
Clock oscillator
Reset input
Boundary scan test interface
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
2000 Jun 14
2
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
1
FEATURES
SAA3500H
•
Digital Audio Broadcast (DAB) full-capacity demodulator
and decoder
•
Supports DAB transmission modes I, II, III and IV
•
Integrated Analog-to-Digital Converter (ADC) for
IF input
•
Digital mixer with on-chip digital Automatic Frequency
Control (AFC) and Automatic Gain Control (AGC)
•
Detectors for null symbol, DAB mode and transmitter
identification
•
On-chip or external synchronization algorithms and
control loops
•
On-chip timing PLL and DCXO
•
Dynamic DAB multiplex reconfiguration supported
•
Equal and unequal error protection for up to
64 sub-channels
•
Fast information channel buffering
•
Simple full capacity output
•
Receiver data interface
•
Serial output for three sub-channels
•
I
2
C-bus or L3-bus control interface.
2 APPLICATIONS
•
Mobile receivers (FM/DAB car radios)
•
Personal Computer add-ons
•
Test and measurement equipment
•
Portable radios.
3
GENERAL DESCRIPTION
The Philips SAA3500H is a Digital Audio Broadcast (DAB)
channel decoder according to the ETSI specification
ETS 300 401. The SAA3500H is a successor to the Philips
FADIC and SIVIC chip set and provides an IF ADC, digital
mixer, full DAB ensemble demodulation and decoding as
well as time and frequency synchronization functions.
Because of the full-speed Viterbi decoding capacity and a
high-speed receiver data output interface, DAB data
reception is not limited by the SAA3500H channel
decoder.
4
QUICK REFERENCE DATA
SYMBOL
PARAMETER
supply voltage
maximum input voltage
DC supply current
clock frequency
ambient temperature
storage temperature
MIN.
3.0
−0.5
−
−
−40
−65
3.3
−
−
24576
+25
−
TYP.
3.6
V
DD
+ 0.5
180
−
+85
+150
MAX.
V
V
mA
kHz
°C
°C
UNIT
V
DD
V
i(max)
I
DD
f
clk
T
amb
T
stg
5
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14
×
20
×
2.7 mm; high stand-off height
VERSION
SOT317-1
SAA3500H
QFP100
2000 Jun 14
3
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
6
BLOCK DIAGRAM
SAA3500H
BYP
AIF
2
INP[9:0]
17
to
8
AGC
SLI
ADCLK
OSCI
OSCO
4
5
IQS
MCLK
19 41
21 20 25 24
ADE
ADC
99
1
AD CONVERTER
(8 BIT)
DIGITAL MIXER
AND FILTERS
NULL DETECTOR,
TIMEBASE,
DCXO
23
22
FSO
FSI
OUT[7:0]
OCLK
OIQ
OCIR
OEN
39 to 32
27
CHANNEL IMPULSE
29
RESPONSE
PROCESSOR
30
31
sync
FAST FOURIER
TRANSFORMATION
BOUNDARY
SCAN TEST
97
95
96
93
98
TMS
TCK
TDI
TDO
TRST
AUTOMATIC FREQUENCY
CONTROL PROCESSOR
DIFFERENTIAL
DEMODULATOR
metrics
SAA3500H
70
62 to 68, 81 to 91
71 to 78
69
61
A17
A[17:0]
D[7:0]
RD
WR
SYMBOL
SELECT
CAPACITY UNIT
SELECT
FREQUENCY & TIME
DE-INTERLEAVER
UNEQUAL/EQUAL
ERROR PROTECTION
CONTROL
MCI
MICROCONTROLLER
INTERFACE
inhibit
VITERBI
DECODER
ERROR FLAG
DETECT/COUNT
FIC
BUFFER
SERIAL OUTPUT
49
to
50 47
46
to
44
55
51
52
54 53
43 56 58 57 59
RDC
RDO
CFIC
RESET
CCLK
SOC SOV[1:3] SFCO
SOD[1:3]
REF
CMODE CDATA
RDE
Fig.1 Block diagram.
2000 Jun 14
4
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
7
PINNING
SYMBOL
ADC
AIF
V
SSA
ADE
V
DDA
INP[0:9]
ADCLK
IQS
BYP
FSI
FSO
SLI
AGC
OSCI
OSCO
MCLK
V
SS
PIN
1
2
3
99
100
8 to 17
19
20
21
22
23
24
25
4
5
41
7, 18,
26, 40,
60, 80
and 94
6, 28,
42 and
79
92
27
29
30
31
51
52
53
54
55
TYPE
input
input
input
input
output
input
input
input
output
output
output
input
output
output
analog-to-digital converter IF input
analog-to-digital converter enable (active LOW)
2048 kHz IF or baseband digital parallel input data (8 or 10 bits)
DESCRIPTION
analog-to-digital converter DC input
SAA3500H
ground analog supply ground
supply analog voltage supply (+3.3 V)
analog-to-digital clock output 8192 kHz if BYP = HIGH, 4096 kHz if BYP = LOW
clock signal indicating I or Q baseband data if BYP = LOW;
signal for swapping I and Q data bytes if BYP = HIGH
IF input stage bypass (active LOW)
frame sync input (LOW indicates DAB null symbol detection)
null detector/frame sync output (LOW indicates DAB null symbol position)
AGC synchronization lock indicator (HIGH if synchronized)
AGC level comparator output (HIGH if input sample > reference level, else LOW)
oscillator or system clock input, 24576 kHz
oscillator output
master clock output, 24576 kHz
supply digital supply ground
V
DD
supply digital voltage supply (+3.3 V)
TEST
OUT[0:7]
OCLK
OIQ
OCIR
OEN
CFIC
CMODE
CDATA
CCLK
RESET
A[17:11]
A[10:0]
WR
RD
A17
D[0:7]
2000 Jun 14
input
output
output
input
input
output
input
I/O
input
input
connect to ground for proper operation
baseband or channel impulse response output
output data clock (negative edge indicates new data)
output I or Q select signal if OCIR = HIGH, or frame trigger if OCIR = LOW
output select: baseband if OCIR = HIGH, CIR if OCIR = LOW
output enable (active LOW)
microcontroller interface signal indicating Fast Information Channel (FIC) processing
microcontroller interface mode input (only L3-bus)
microcontroller interface serial data I
2
C-bus or L3-bus (5 V tolerant)
microcontroller interface clock input I
2
C-bus or L3-bus
chip reset input (active LOW)
address outputs external RAM
address outputs external RAM
write data to RAM (active LOW)
read data from RAM (active LOW)
address bit 17 inverted for second RAM (128k
×
8)
data input/output external RAM
5
32 to 39 output
62 to 68 output
81 to 91 output
61
69
70
output
output
output
71 to 78 I/O
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
