INTEGRATED CIRCUITS
DATA SHEET
SAA4978H
Picture Improved Combined
Network (PICNIC)
Product specification
Supersedes data of 1998 Oct 07
File under Integrated Circuits, IC02
1999 May 03
Philips Semiconductors
Product specification
Picture Improved Combined Network
(PICNIC)
CONTENTS
1
2
3
4
5
6
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
FEATURES
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING INFORMATION
FUNCTIONAL DESCRIPTION
Analog input blocks
Gain elements for automatic gain control (9 dB
range)
Clamp circuit, clamping Y to digital level 32 and
UV to 0 (2’s complement)
Analog anti-aliasing prefilter
9-bit analog-to-digital conversion
Digital processing blocks
Overflow detection
Y delay
Transient noise suppression
Non-linear phase filter after ADC
4 MHz notch
Digital clamp correction for UV
4 : 4 : 4 downsampled to 4 : 2 : 2 or 4 : 1 : 1
Bus A format: interface formatting, timed with
enabling signal (see Table 1 and Fig.9)
Bus B format (see Table 1 and Fig.9)
Time base correction and sample rate
conversion
Noise reduction
Histogram
Subtitle detection
Black bar detection
Bus C format (see Table 1)
Bus D reformatter: the various input formats
are all converted to the internal 9 bits 4 : 2 : 2
(see Table 1)
Peaking
Non-linear phase filter before DAC
DCTI
Border blank
Analog output blocks
Triple 10-bit digital-to-analog conversion
Analog anti-aliasing post-filter
PLL
SNERT
PSP
Microcontroller
Board level testability
Power-on reset
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
17
SAA4978H
CONTROL REGISTER DESCRIPTION
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
APPLICATION
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
7.2.17
7.2.18
7.2.19
7.2.20
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
1999 May 03
2
Philips Semiconductors
Product specification
Picture Improved Combined Network
(PICNIC)
1
FEATURES
SAA4978H
•
Clamp
•
Analog AGC
•
Triple YUV 9-bit Analog-to-Digital Converter (ADC)
•
Triple bypassable analog anti-alias filter
•
4 MHz notch filter
•
Non-linear phase filter after ADC
•
4 : 1 : 1 or 4 : 2 : 2 digital processing
•
4 : 1 : 1 or 4 : 2 : 2 selectable I/O interface
•
Asynchronous digital input
•
Time base correction
•
Histogram analysis
•
Histogram modification
•
Subtitle detection
•
Black bar detection
•
Line memory based noise reduction (spatial)
•
Noise level measurement
•
Clamp noise reduction
•
Dynamic peaking
•
Energy measurement
•
Multi Picture-In-Picture (multi PIP) decimation
•
Differential Pulse Code Modulation (DPCM) data
decompression for colour
3
QUICK REFERENCE DATA
SYMBOL
V
DDA
V
DDD
I
DDA
I
DDD
f
clk
S/N
4
PARAMETER
analog supply voltage
digital supply voltage
analog supply current
digital supply current
clock frequency
signal-to-noise ratio
default settings
V
DDA
= 3.45 V
V
DDD
= 3.6 V
CONDITIONS
MIN.
3.15
3.0
−
−
−
50
TYP.
3.3
3.3
145
210
16
−
MAX.
3.45
3.6
180
270
−
−
UNIT
V
V
mA
mA
MHz
dB
2
GENERAL DESCRIPTION
The SAA4978H is a monolithic integrated circuit suitable
either for 1f
H
or 2f
H
applications that contain a large variety
of picture improvement functions. It combines
analog-to-digital and digital-to-analog conversion for YUV
signals, digital processing, line-locked clock regeneration
and an 80C51 microcontroller core in one IC.
•
2D-peaking and coring
•
Non-linear phase filter before DAC
•
Coaxial Transceiver Interface (CTI)
•
Triple 10-bit Digital-to-Analog Converter (DAC)
•
Triple bypassable analog reconstruction filter
•
Embedded microcontroller (80C51 core)
•
Programmable signal positioner
•
SNERT interface
•
I
2
C-bus user control interface
•
Boundary Scan Test (BST).
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
QFP160
DESCRIPTION
plastic quad flat package; 160 leads (lead length 1.6 mm);
body 28
×
28
×
3.4 mm; high stand-off height
VERSION
SOT322-2
SAA4978H
1999 May 03
3
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1999 May 03
BGEXT
17
BAND GAP
REFERENCES
SYNCHRONIZE
DITHER
Y
DELAY
MUX
MAJORITY
FOLLOWER
FILTER
4 MHz
NOTCH
5
DITHER
REFORMATTER
5
FORMATTER
DOWNSAMPLER
11
UPSAMPLER
MUX
DOWNSAMPLER
DITHER
10
B
MUX
NON-LINEAR
PHASE
FILTER
A
Ref L
Ref H
various
bias controls
3-STATE
62
53 to 61
43 to 51 84 to 76 75 to 67 66 85
Philips Semiconductors
BLOCK DIAGRAM
VDDD1 to
VDDD4
WEA
CLKAS
VSSD1 to
VSSD4
YA0
to
YA8
WEB
UVA0
to
UVA8
UVB0
to
UVB8
YB0
to
YB8
64, 87,
100, 135
64, 90,
134, 139
DIFFIN
21
YIN
23
CLAMP
TRIPLE
AGC
9-BIT
TRIPLE
ANALOG
PREFILTER
ADC
TRIPLE
9-BIT
UIN
UV
CLAMP
CORRECTION
25
TIME BASE
CORRECTION/
SAMPLE
RATE
CONVERTER
VIN
26
Picture Improved Combined Network
(PICNIC)
CLP
bus A
RED
BORDER
CLP
WEC
IEC
HREF
PIXREP
WEA
BLANKING
HA
bus B
OVERFLOW
DETECTOR
SKEWEN
SKEW
4
PSP
18
19
29
30
158
157
10
HDFL VDFL
VA
HREFEXT
INT1
INT0
FBL
VDDA1 to
VDDA4
11, 22, 24, 31
SAA4978H
VSSA1 to
VSSA4
13, 16, 27, 32
C
D
BST/TEST
E
F
G
MHB172
36
37
38
39
40
41
TEST TRST TMS
TDI
TDO TCK
Standard bus width in data path is 9 bits; exceptions are marked.
Product specification
SAA4978H
Fig.1 Block diagram (continued in Fig.2).
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1999 May 03
YC8
to
WEC IEC YC0
UVD0
to
UVD8
RED
UVC8
to
UVC0
YD0
to
YD8
113
3-STATE
UNDITHER
DITHER
MUX
DOWNSAMPLER
DITHER
5
5
REFORMATTER
MUX
UPSAMPLER
10
MUX
DPCM DECODER
10
DCTI
DITHER
4
8
4
DPCM
CODER
bus C
bus D
PIXREP
BORDER
AUXILIARY
RAM
PROGRAM
ROM
BLANKING
FORMATTER
BORDER
BLANK
DAC
TRIPLE
10-BIT
TRIPLE
ANALOG
POST-FILTER
14
UOUT
15
DYNAMIC 10
PEAKING
12
NON-LINEAR 10
PHASE
FILTER
YOUT
SPECTRAL
MEASUREMENT
112
114 to 122
124 to 132
91
to 99
101 to 109
110
VOUT
Philips Semiconductors
SPECTRAL
MEASUREMENT
SUBTITLE
DETECTION
NOISE
ESTIMATION
BLACK BAR
DETECTION
A
NOISE
REDUCTION
HISTOGRAM
MODIFICATION
Picture Improved Combined Network
(PICNIC)
B
5
SAA4978H
CL16
CL16
CL16
HREF
80C51 MICROCONTROLLER CORE
P1.5
WATCHDOG
P3.5 P3.4 P1.2 P1.3 P1.7 P1.6 RST
bone
FREQUENCY
GUARD
OR
9
5
4
6
7
42, 63, 86,
111, 133, 3
52, 123, 148
88
89
T0
RSTR
SCL
RST
RSTW
SDA
WDRST
VSSO1
to
VSSO6
VDDO1
to
VDDO3
SPECIAL FUNCTION
REGISTERS
VARIOUS
REGISTERS
C
SKEWEN
SKEW
CL16
CL32
D
DATA8
PLL
P1.1
INT1 INT0 P1.4
EA PSEN
E
CRYSTAL
OSCILLATOR
28
34
35
MHB173
F
G
1
2
140 149
to
to
147 156 136 137 138 160 159 8
SNDA SNCL
P2.7 P0.7 EA
ALE
to
to
T1
PSEN
P2.0 P0.0
CLK16 CLK32 HA
OSCI
OSCO
Standard bus width in data path is 9 bits; exceptions are marked.
Product specification
SAA4978H
Fig.2 Block diagram (continued from Fig.1).
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