Da ta S h e et, V2 .0 , De c. 2 00 0
C165
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
Edition 2000-12
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 2000.
All Rights Reserved.
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Da ta S h e et, V2 .0 , De c. 2 00 0
C165
16-Bit Single-Chip Microcontroller
Microcontrollers
N e v e r
s t o p
t h i n k i n g .
C165
Revision History:
Previous Version:
2000-12
1998-12
01.96
07.95
09.94
Update 0.5µ technology
3 Volt Addendum
25 MHz Addendum
Data Sheet
V2.0
Page
All
2
6ff
14
32
33
34f
36f
38f
40ff
45, 55, 65
48, 58, 66
Subjects (major changes since last revision)
Converted to Infineon layout
ROM derivatives removed, 25-MHz derivatives and 3 V derivatives
included
Pin numbers for TQFP added
Address window arbitration and master/slave mode introduced
New standard layout for section “Absolute Maximum Ratings”
Section “Operating Conditions” added
Parameter “RSTIN pullup” replaced by “RSTIN current”
DC Characteristics for reduced supply voltage added
Separate specification for power consumption with greatly improved values
Description of clock generation improved
Timing adapted to 25 MHz
Timing for reduced supply voltage added
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Please send your proposal (including a reference to this document) to:
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16-Bit Single-Chip Microcontroller
C166 Family
C165
C165
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplication (16
×
16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 28 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via prescaler or via direct clock input
• On-Chip Memory Modules
– 2 KBytes On-Chip Internal RAM (IRAM)
• On-Chip Peripheral Modules
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
• Up to 16 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
• Idle and Power Down Modes
• Programmable Watchdog Timer
• Up to 77 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• Power Supply: the C165 can operate from a 5 V or a 3 V power supply
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 100-Pin MQFP Package (0.65 mm pitch)
• 100-Pin TQFP Package (0.5 mm pitch)
Data Sheet
1
V2.0, 2000-12
DSP 与 ARM 处理器
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