Philips Semiconductors
Product specification
Digital video encoder
CONTENTS
1
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
8
8.1
8.2
9
10
11
11.1
FEATURES
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Reset conditions
Input formatter
RGB LUT
Cursor insertion
RGB Y-C
B
-C
R
matrix
Horizontal scaler
Vertical scaler and anti-flicker filter
FIFO
Border generator
Oscillator and Discrete Time Oscillator (DTO)
Low-pass Clock Generation Circuit (CGC)
Encoder
RGB processor
Triple DAC
Timing generator
I
2
C-bus interface
Programming the SAA7102; SAA7103
Input levels and formats
Bit allocation map
I
2
C-bus format
Slave receiver
Slave transmitter
BOUNDARY SCAN TEST
Initialization of boundary scan circuit
Device identification codes
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
Teletext timing
14.2
14.3
14.4
14.5
15
16
17
18
12
12.1
12.2
13
14
14.1
SAA7102; SAA7103
APPLICATION INFORMATION
Analog output voltages
Suggestions for a board layout
PACKAGE OUTLINES
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
2001 Sep 25
2
Philips Semiconductors
Product specification
Digital video encoder
1
FEATURES
SAA7102; SAA7103
•
Digital PAL/NTSC encoder with integrated high quality
scaler and anti-flicker filter for TV output from a PC
•
27 MHz crystal-stable subcarrier generation
•
Maximum graphics pixel clock 45 MHz at double edged
clocking, synthesized on-chip or from external source
•
Up to 800
×
600 graphics data at 60 Hz or 50 Hz with
programmable underscan range
•
Three Digital-to-Analog Converters (DACs) at 27 MHz
sample rate for CVBS (BLUE, C
B
), VBS (GREEN,
CVBS) and C (RED, C
R
) (signals in parenthesis are
optional); all at 10-bit resolution
•
Non-interlaced C
B
-Y-C
R
or RGB input at maximum
4 : 4 : 4 sampling
•
Downscaling from 1 : 1 to 1 : 2 and up to 20% upscaling
•
Optional interlaced C
B
-Y-C
R
input Digital Versatile Disk
(DVD)
•
Optional non-interlaced RGB output to drive second
VGA monitor (bypass mode, maximum 45 MHz)
•
3
×
256 bytes RGB Look-Up Table (LUT)
•
Support for hardware cursor
•
Programmable border colour of underscan area
•
On-chip 27 MHz crystal oscillator (3rd-harmonic or
fundamental 27 MHz crystal)
•
Fast I
2
C-bus control port (400 kHz)
•
Encoder can be master or slave
•
Programmable horizontal and vertical input
synchronization phase
•
Programmable horizontal sync output phase
•
Internal Colour Bar Generator (CBG)
•
Optional support of various Vertical Blanking Interval
(VBI) data insertion
•
Macrovision Pay-per-View copy protection system
rev. 7.01 and rev. 6.1 as option; this applies to SAA7102
only. The device is protected by USA patent numbers
4631603, 4577216 and 4819098 and other intellectual
property rights. Use of the Macrovision anti-copy
process in the device is licensed for non-commercial
home use only. Reverse engineering or disassembly is
prohibited. Please contact your nearest Philips
Semiconductors sales office for more information.
•
Power-save modes
•
Joint Test Action Group (JTAG) boundary scan test
•
Monolithic CMOS 3.3 V device, 5 V tolerant I/Os
•
QFP44 and BGA156 packages
•
Same footprint as SAA7108E; SAA7109E.
2
GENERAL DESCRIPTION
The SAA7102; SAA7103 is used to encode PC graphics
data at maximum 800
×
600 resolution to PAL (50 Hz) or
NTSC (60 Hz) video signals. A programmable scaler and
interlacer ensures properly sized and flicker-free TV
display as CVBS or S-video output.
Alternatively, the three Digital-to-Analog Converters
(DACs) can output RGB signals together with a TTL
composite sync to feed SCART connectors.
When the scaler/interlacer is bypassed, a second VGA
monitor can be connected to the RGB outputs and
separate H and V-syncs as well, thereby serving as an
auxiliary monitor at maximum 800
×
600 resolution/60 Hz
(PIXCLK < 45 MHz).
The device includes a sync/clock generator and on-chip
DACs.
2001 Sep 25
3
嵌入式系统
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