INTEGRATED CIRCUITS
DATA SHEET
SAA7118
Multistandard video decoder with
adaptive comb filter and component
video input
Preliminary specification
Supersedes data of 2000 Nov 27
File under Integrated Circuits, IC22
2001 May 30
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive
comb filter and component video input
CONTENTS
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
2
3
4
5
6
7
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
10
10.1
10.2
FEATURES
Video acquisition/clock
Video decoder
Component video processing
Video scaler
Vertical Blanking Interval (VBI) data decoder
and slicer
Audio clock generation
Digital I/O interfaces
Miscellaneous
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Decoder
Component video processing
Decoder output formatter
Scaler
VBI-data decoder and capture
(subaddresses 40H to 7FH)
Image port output formatter
(subaddresses 84H to 87H)
Audio clock generation
(subaddresses 30H to 3FH)
INPUT/OUTPUT INTERFACES AND PORTS
Analog terminals
Audio clock signals
Clock and real-time synchronization signals
Interrupt handling
Video expansion port (X-port)
Image port (I-port)
Host port for 16-bit extension of video data I/O
(H-port)
Basic input and output timing diagrams I-port
and X-port
BOUNDARY SCAN TEST
Initialization of boundary scan circuit
Device identification codes
16
16.1
16.2
16.3
16.4
16.5
17
18
18.1
18.2
18.3
18.4
18.5
19
20
21
22
11
12
13
14
15
15.1
15.2
15.3
15.4
15.5
15.6
15.7
LIMITING VALUES
SAA7118
THERMAL CHARACTERISTICS
CHARACTERISTICS
APPLICATION INFORMATION
I
2
C-BUS DESCRIPTION
I
2
C-bus format
I
2
C-bus details
Programming register RGB/Y-P
B
-P
R
component input processing
Interrupt mask registers
Programming register audio clock generation
Programming register VBI-data slicer
Programming register interfaces and scaler
part
PROGRAMMING START SET-UP
Decoder part
Component video part and interrupt mask
Audio clock generation part
Data slicer and data type control part
Scaler and interfaces
PACKAGE OUTLINES
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
DEFINITIONS
DISCLAIMERS
PURCHASE OF PHILIPS I
2
C COMPONENTS
2001 May 30
2
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive
comb filter and component video input
1
1.1
FEATURES
Video acquisition/clock
SAA7118
•
Up to sixteen analog CVBS, split as desired (all of the
CVBS inputs optionally can be used to convert e.g.
Vestigial Side Band (VSB) signals)
•
Up to eight analog Y + C inputs, split as desired
•
Up to four analog component inputs, with embedded or
separate sync, split as desired
•
Four on-chip anti-aliasing filters in front of the
Analog-to-Digital Converters (ADCs)
•
Automatic Clamp Control (ACC) for CVBS, Y and C
(or VSB) and component signals
•
Switchable white peak control
•
Four 9-bit low noise CMOS ADCs running at twice the
oversampling rate (27 MHz)
•
Fully programmable static gain or Automatic Gain
Control (AGC), matching to the particular signal
properties
•
On-chip line-locked clock generation in accordance with
“ITU 601”
•
Requires only one crystal (32.11 or 24.576 MHz) for all
standards
•
Horizontal and vertical sync detection.
1.2
Video decoder
•
Independent gain and offset adjustment for raw data
path.
1.3
Component video processing
•
RGB component inputs
•
Y-P
B
-P
R
component inputs
•
Fast blanking between CVBS and synchronous
component inputs
•
Digital RGB to Y-C
B
-C
R
matrix.
1.4
Video scaler
•
Horizontal and vertical downscaling and upscaling to
randomly sized windows
•
Horizontal and vertical scaling range: variable zoom to
1
⁄
(icon) (note: H and V zoom are restricted by the
64
transfer data rates)
•
Anti-alias and accumulating filter for horizontal scaling
•
Vertical scaling with linear phase interpolation and
accumulating filter for anti-aliasing (6-bit phase
accuracy)
•
Horizontal phase correct up and downscaling for
improved signal quality of scaled data, especially for
compression and video phone applications, with 6-bit
phase accuracy (1.2 ns step width)
•
Two independent programming sets for scaler part, to
define two ‘ranges’ per field or sequences over frames
•
Fieldwise switching between decoder part and
expansion port (X-port) input
•
Brightness, contrast and saturation controls for scaled
outputs.
1.5
Vertical Blanking Interval (VBI) data decoder
and slicer
•
Digital PLL for synchronization and clock generation
from all standards and non-standard video sources e.g.
consumer grade VTR
•
Automatic detection of any supported colour standard
•
Luminance and chrominance signal processing for
PAL B, G, D, H, I and N, combination PAL N, PAL M,
NTSC M, NTSC-Japan, NTSC 4.43 and SECAM
•
Adaptive 2/4-line comb filter for two dimensional
chrominance/luminance separation, also with VTR
signals
– Increased luminance and chrominance bandwidth for
all PAL and NTSC standards
– Reduced cross colour and cross luminance artefacts
•
PAL delay line for correcting PAL phase errors
•
Brightness Contrast Saturation (BCS) adjustment,
separately for composite and baseband signals
•
User programmable sharpness control
•
Detection of copy-protected signals according to the
macrovision standard, indicating level of protection
•
Versatile VBI-data decoder, slicer, clock regeneration
and byte synchronization e.g. for World Standard
Teletext (WST), North-American Broadcast Text
System (NABTS), close caption, Wide Screen Signalling
(WSS) etc.
2001 May 30
3
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive
comb filter and component video input
1.6
Audio clock generation
2
APPLICATIONS
SAA7118
•
Generation of a field-locked audio master clock to
support a constant number of audio clocks per video
field
•
Generation of an audio serial and left/right (channel)
clock signal.
1.7
Digital I/O interfaces
•
PC-video capture and editing
•
Personal video recorders (time shifting)
•
Cable, terrestrial, and satellite set-top boxes
•
Internet terminals
•
Flat-panel monitors
•
DVD-recordable players
•
AV-ready hard-disk drivers
•
Digital televisions/scan conversion
•
Video surveillance/security
•
Video editing/post production
•
Video phones
•
Video projectors
•
Digital VCRs.
3
GENERAL DESCRIPTION
•
Real-time signal port (R port), inclusive continuous
line-locked reference clock and real-time status
information supporting RTC level 3.1 (refer to document
“RTC Functional Specification”
for details)
•
Bidirectional expansion port (X-port) with half duplex
functionality (D1), 8-bit Y-C
B
-C
R
– Output from decoder part, real-time and unscaled
– Input to scaler part, e.g. video from MPEG decoder
(extension to 16-bit possible)
•
Video image port (I-port) configurable for 8-bit data
(extension to 16-bit possible) in master mode (own
clock), or slave mode (external clock), with auxiliary
timing and handshake signals
•
Discontinuous data streams supported
•
32-word
×
4-byte FIFO register for video output data
•
28-word
×
4-byte FIFO register for decoded VBI-data
output
•
Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 Y-C
B
-C
R
output
•
Scaled 8-bit luminance only and raw CVBS data output
•
Sliced, decoded VBI-data output.
1.8
Miscellaneous
The SAA7118 is a video capture device for applications at
the image port of VGA controllers.
Philips X-VIP is a new multistandard comb filter video
decoder chip with additional component processing,
providing high quality, optionally scaled, video.
The SAA7118 is a combination of a four-channel analog
preprocessing circuit including source selection,
anti-aliasing filter and ADC with succeeding decimation
filters from 27 to 13.5 MHz data rate. Each preprocessing
channel comes with an automatic clamp and gain control.
The SAA7118 combines a Clock Generation Circuit
(CGC), a digital multistandard decoder containing
two-dimensional chrominance/luminance separation by an
adaptive comb filter and a high performance scaler,
including variable horizontal and vertical up and
downscaling and a brightness, contrast and saturation
control circuit.
•
Power-on control
•
5 V tolerant digital inputs and I/O ports
•
Software controlled power saving standby modes
supported
•
Programming via serial I
2
C-bus, full read back ability by
an external controller, bit rate up to 400 kbits/s
•
Boundary scan test circuit complies with the
“IEEE Std.
1149.b1 - 1994”.
2001 May 30
4
Philips Semiconductors
Preliminary specification
Multistandard video decoder with adaptive
comb filter and component video input
It is a highly integrated circuit for desktop video and similar
applications. The decoder is based on the principle of
line-locked clock decoding and is able to decode the colour
of PAL, SECAM and NTSC signals into ITU 601
compatible colour component values. The SAA7118
accepts CVBS or S-video (Y/C) as analog inputs from TV
or VCR sources, including weak and distorted signals as
well as baseband component signals Y-P
B
-P
R
or RGB. An
expansion port (X-port) for digital video (bidirectional half
duplex, D1 compatible) is also supported to connect to
MPEG or video phone codec. At the so called image port
(I-port) the SAA7118 supports 8 or 16-bit wide output data
with auxiliary reference data for interfacing to VGA
controllers.
The target application for the SAA7118 is to capture and
scale video images, to be provided as digital video stream
through the image port of a VGA controller, for capture to
system memory, or just to provide digital baseband video
to any picture improvement processing.
4
QUICK REFERENCE DATA
SYMBOL
V
DDD
V
DDDC
V
DDA
T
amb
P
A+D
Note
PARAMETER
digital supply voltage
digital core supply voltage
analog supply voltage
ambient temperature
analog and digital power dissipation
note 1
CONDITIONS
MIN.
3.0
3.0
3.1
0
−
TYP.
3.3
3.3
3.3
−
1.1
SAA7118
The SAA7118 also provides a means for capturing the
serially coded data in the vertical blanking interval
(VBI-data). Two principal functions are available:
1. To capture raw video samples, after interpolation to
the required output data rate, via the scaler
2. A versatile data slicer (data recovery) unit.
The SAA7118 also incorporates field-locked audio clock
generation. This function ensures that there is always the
same number of audio samples associated with a field, or
a set of fields. This prevents the loss of synchronization
between video and audio during capture or playback.
All of the ADCs may be used to digitize a VSB signal for
subsequent decoding; a dedicated output port and a
selectable VSB clock input is provided.
The circuit is I
2
C-bus controlled (full write/read capability
for all programming registers, bit rate up to 400 kbits/s).
MAX.
3.6
3.6
3.5
70
1.35
V
V
V
°C
W
UNIT
1. Power dissipation is measured in component mode (four ADCs active) and 8-bit image port output mode, expansion
port is 3-stated.
5
ORDERING INFORMATION
TYPE
NUMBER
SAA7118E
SAA7118H
PACKAGE
NAME
BGA156
QFP160
DESCRIPTION
plastic ball grid array package; 156 balls; body 15
×
15
×
1.15 mm
plastic quad flat package; 160 leads (lead length 1.6 mm);
body 28
×
28
×
3.4 mm; high stand-off height
VERSION
SOT472-1
SOT322-2
2001 May 30
5
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