Philips Semiconductors
Product specification
Digital video encoder
FEATURES
•
Monolithic CMOS 3.3 V device, 5 V I
2
C-bus optionally
•
Digital PAL/NTSC encoder
•
System pixel frequency 13.5 MHz
•
54 MHz double-speed multiplexed D1 interface capable
of splitting data into two separate channels (encoded
and baseband)
•
Four Digital-to-Analog Converters (DACs) for CVBS
(CSYNC, VBS), RED (Cr, C), GREEN (Y, VBS) and
BLUE (Cb, CVBS) two times oversampled (signals in
parenthesis are optionally). RED (Cr), GREEN (Y) and
BLUE (Cb) signal outputs with 9-bit resolution, whereas
all other signal outputs have 10-bit resolution; CSYNC is
an advanced composite sync on the CVBS output for
RGB display centring.
•
Real-time control of subcarrier
•
Cross-colour reduction filter
•
Closed captioning encoding and World Standard
Teletext (WST) and North-American Broadcast Text
System (NABTS) teletext encoding including sequencer
and filter
•
Copy Generation Management System (CGMS)
encoding (CGMS described by standard CPR-1204 of
EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via
the I
2
C-bus
•
Fast I
2
C-bus control port (400 kHz)
•
Line 23 Wide Screen Signalling (WSS) encoding
•
Video Programming System (VPS) data encoding in
line 16 (CCIR line count)
•
Encoder can be master or slave
•
Programmable horizontal and vertical input
synchronization phase
•
Programmable horizontal sync output phase
•
Internal Colour Bar Generator (CBG)
SAA7126H; SAA7127H
•
Macrovision Pay-per-View copy protection system
rev. 7.01 and rev. 6.1 as option; ‘handsfree’ Macrovision
pulse support through on-chip timer for pulse amplitude
modulation; this applies to SAA7126H only. The device
is protected by USA patent numbers 4631603, 4577216
and 4819098 and other intellectual property rights.
Use of the Macrovision anti-copy process in the device
is licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited. Please
contact your nearest Philips Semiconductors sales
office for more information.
•
Controlled rise/fall times of output syncs and blanking
•
On-chip crystal oscillator (3rd-harmonic or fundamental
crystal)
•
Down mode (low output voltage) or power-save mode of
DACs
•
QFP44 package.
GENERAL DESCRIPTION
The SAA7126H; SAA7127H encodes digital Cb-Y-Cr
video data to an NTSC or PAL CVBS or S-video signal.
Simultaneously, RGB or bypassed but interpolated
Cb-Y-Cr signals are available via three additional
Digital-to-Analog Converters (DACs). The circuit at a
54 MHz multiplexed digital D1 input port accepts two CCIR
compatible Cb-Y-Cr data streams with 720 active pixels
per line in 4 : 2 : 2 multiplexed formats, for example MPEG
decoded data with overlay and MPEG decoded data
without overlay, whereas one data stream is latched at the
rising, the other one at the falling clock edge.
It includes a sync/clock generator and on-chip DACs.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA7126H
SAA7127H
QFP44
DESCRIPTION
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10
×
10
×
1.75 mm
VERSION
SOT307-2
1999 May 31
2
Philips Semiconductors
Product specification
Digital video encoder
PINNING
SYMBOL TYPE PIN
RES
SP
AP
LLC1
V
SSD1
V
DDD1
RCV1
RCV2
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
V
DDD2
V
SSD2
RTCI
−
I
I
I
−
−
I/O
I/O
I
I
I
I
I
I
I
I
−
−
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
digital supply voltage 2
digital ground 2
reserved pin; do not connect
DESCRIPTION
SAA7126H; SAA7127H
test pin; connected to digital ground for normal operation
test pin; connected to digital ground for normal operation
line-locked clock input; this is the 27 MHz master clock
digital ground 1
digital supply voltage 1
raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal
raster control 2 for video port; this pin provides an HS pulse of programmable length or
receives an HS pulse
double-speed 54 MHz MPEG port; it is an input for
“CCIR 656”
style multiplexed Cb-Y-Cr
data; data is sampled on the rising and falling clock edge; data sampled on the rising edge is
then sent to the encoding part of the device; data sampled on the falling edge is sent to the
RGB part of the device (or vice versa, depending on programming)
real-time control input (I
2
C-bus register SRES = 0): if the LLC1 clock is provided by an
SAA7111 or SAA7151B, RTCI should be connected to the RTCO pin of the respective
decoder to improve the signal quality. Sync reset input (I
2
C-bus register SRES = 1): a HIGH
impulse resets synchronization of the encoder (first field, first line).
sense input for I
2
C-bus voltage; connect to I
2
C-bus supply
select I
2
C-bus address; LOW selects slave address 88H, HIGH selects slave address 8CH
analog ground 1 for RED (Cr) (C) and GREEN (Y) (VBS) outputs
analog output of RED (Cr) or (C) signal
not connected
analog supply voltage 1 for RED (Cr) (C) output
analog output of GREEN (Y) or (VBS) signal
not connected
analog supply voltage 2 for GREEN (Y) (VBS) output
analog output of BLUE (Cb) or (CVBS) signal
analog output of CVBS (CSYNC) or (VBS) signal
analog supply voltage 3 for BLUE (Cb) (CVBS) and CVBS (CSYNC) (VBS) outputs
analog ground 2 for BLUE (Cb) (CVBS) and CVBS (CSYNC) (VBS) outputs
analog ground 3 for the DAC reference ladder and the oscillator
crystal oscillator output
crystal oscillator input; if the oscillator is not used, this pin should be connected to ground
analog supply voltage 4 for the DAC reference ladder and the oscillator
V
DD(I2C)
SA
V
SSA1
RED
n.c.
V
DDA1
GREEN
n.c.
V
DDA2
BLUE
CVBS
V
DDA3
V
SSA2
V
SSA3
XTAL
XTALI
V
DDA4
−
I
−
O
−
−
O
−
−
O
O
−
−
−
O
I
−
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1999 May 31
4
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