INTEGRATED CIRCUITS
DATA SHEET
SAA7157
Clock signal generator circuit for
digital TV systems (SCGC)
Product specification
File under Integrated Circuits, IC02
May 1992
Philips Semiconductors
Product specification
Clock signal generator circuit for digital
TV systems (SCGC)
FEATURES
•
Clock generation suitable for digital TV systems (line-locked)
•
PLL frequency multiplier to generate 4 times of input frequency
SAA7157
•
Dividers to generate clocks LL1.5A, LL1.5B, LL3A and LL3B (4th and 2nd multiples of input frequency)
•
PLL mode or VCO mode selectable
•
Reset control and power fail detection
•
Suitable for applications with feature box and picture memory
GENERAL DESCRIPTION
The SAA7157 generates all clock signals required for a digital TV system suitable for the SAA715x family and the
SAA7199B (DENC). The circuit operates in either the phase-locked loop mode (PLL) or voltage controlled oscillator
mode (VCO).
QUICK REFERENCE DATA
SYMBOL
V
DDA
V
DDD
I
DDA
I
DDD
V
LFCO
f
i
V
I
V
O
T
amb
PARAMETER
analog supply voltage (pin 5)
digital supply voltage (pins 8, 17)
analog supply current
digital supply current
LFCO input voltage
(peak-to-peak value)
input frequency range
input voltage LOW
input voltage HIGH
output voltage LOW
output voltage HIGH
operating ambient temperature range
MIN. TYP. MAX. UNIT
4.5
4.5
3
10
1
6.0
0
2.0
0
2.6
0
5.0
5.0
-
-
-
-
-
-
-
-
-
5.5
5.5
9
60
V
DDA
7.25
0.8
V
DDD
0.6
V
DDD
70
V
V
mA
mA
V
MHz
V
V
V
V
°C
ORDERING INFORMATION
EXTENDED
TYPE NUMBER
SAA7157
SAA7157T
Note
1. SOT146-1; 1996 December 17.
2. SOT163-1; 1996 December 17.
PACKAGE
PINS
20
20
PIN POSITION
DIL
mini-pack (SO20)
MATERIAL
plastic
plastic
CODE
SOT146
(1)
SOT163A
(2)
May 1992
2
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
handbook, full pagewidth
SAA7157
VDDA
5
VDDD1 VDDD2
8
17
MS
1
LOOP
FILTER
MS = LOW
VCO
7
LL1.5A
(LL27A)
LL1.5B
(LL27B)
LL3A
SAA7157
FREQUENCY
DIVIDER
1:2
FREQUENCY
DIVIDER
1:2
10
14
PHASE
DETECTOR
20
LL3B
DELAY
PRE-FILTER
AND
PULSE
SHAPER
15
CREF
LFCO
11
POWER-ON
RESET
12
RESN
LFCO2
CE
19
2
16
LFCOSEL
3
PORD
4
VSSA
6, 9, 13, 18
VSSD
MEH452
Fig.1 Block diagram.
FUNCTIONAL DESCRIPTION
The SAA7157 generates all clock signals required for a
digital TV system suitable for the SAA715x family
consisting of an 8-bit analog-to-digital converter (ADC8),
digital video multistandard decoder (DMSD2) and video
enhancement and D/A processor circuit (VEDA). Optional
extras (feature box, video memory etc.) can be driven via
external buffers, advantageous for a digital TV system
based on display standard conversion concepts.
The 6.75 MHz input signal LFCO (triangular waveform)
coming from the DMSD or LFCO2 is multiplied to 27 MHz
by the PLL (including phase detector, loop filter, VCO and
frequency divider) and output on LL1.5A (pin 7) and
LL1.5B (pin 10). The 13.5 MHz frequencies are generated
by dividers using ratio of 1:2 and are output on LL3A (pin
14) and LL3B (pin 20).
The rectangular output signals have 50% duty factor.
Outputs with equal frequency may be connected together
externally. The clock outputs go HIGH during power-on
reset (and chip enable) to ensure that no output clock
signals are available before the PLL has locked-on.
Mode select MS
The LFCO input signal is directly connected to the VCO at
MS = HIGH. The circuit operates as an oscillator and
frequency divider. This function is not tested.
Source select LFCOSEL
Line frequency control signal (LFCO) is selected by
LFCOSEL input.
LFCOSEL = LOW:
signal from LFCO (pin 11) is selected.
LFCOSEL = HIGH:
signal from LFCO2 (pin 19) is selected.
This function is not tested.
Chip enable CE
The buffer outputs are enabled and RESN is set to HIGH
by
CE = HIGH (Fig.4).
CE = LOW sets the clock outputs HIGH and RESN output
LOW.
May 1992
3
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
CREF output
SAA7157
TV2 digital clock reference output signal. Clock qualifier signal to TV system with 2 times of LFCO or LFCO2 frequency.
Power-on reset
Power-on reset is activated at power-on, when the supply voltage decreases below 3.5 V (Fig.4) or when chip enable is
done. The indicator output RESN is LOW for a time determined by capacitor on pin 3. The RESN signal can be applied
to reset other circuits of this digital TV system.
The LFCO or LFCO2 input signals have to be applied before RESN becomes HIGH.
PINNING
SYMBOL
MS
CE
PORD
V
SSA
V
DDA
V
SSD1
LL1.5A
V
DDD1
V
SSD2
LL1.5B
LFCO
RESN
V
SSD3
LL3A
CREF
LFCOSEL
V
DDD2
V
SSD4
LFCO2
LL3B
Note
1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of horizontal frequency.
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DESCRIPTION
mode select input (LOW = PLL mode)
chip enable /reset (HIGH = outputs enabled)
power-on reset delay, dependent on external capacitor
analog ground (0 V)
analog supply voltage (+5 V)
digital ground 1 (0 V)
line-locked clock output signal 1.5A (4 times f
LFCO
)
digital supply voltage 1 (+5 V)
digital ground 2 (0 V)
line-locked clock output signal 1.5B (4 times f
LFCO
)
line-locked frequency control input signal 1
reset output (active-LOW, Fig.4)
digital ground 3 (0 V)
line-locked clock output signal 3A (2 times f
LFCO
)
clock reference output, qualifier signal (2 times f
LFCO
)
LFCO source select (LOW = LFCO selected)
(1)
digital supply voltage 2 (+5 V)
digital ground 4 (0 V)
line-locked frequency control input signal 2
(1)
line-locked clock output signal 3B (2 times f
LFCO
)
May 1992
4
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
PIN CONFIGURATION
SAA7157
Fig.2 Pin configuration.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); ground pins as well as supply pins together
connected.
SYMBOL
V
DDA
V
DDD
V
diff GND
V
O
P
tot
T
stg
T
amb
V
ESD
Notes
1. Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
recommended to take normal handling precautions appropriate to
“Handling MOS devices”.
analog supply voltage (pin 5)
digital supply voltage (pins 8 and 17)
difference voltage V
DDA
−
V
DDD
output voltage (I
OM
= 20 mA)
total power dissipation (DIL20)
storage temperature range
operating ambient temperature range
electrostatic handling
(1)
for all pins
PARAMETER
MIN.
−0.5
−0.5
-
−0.5
0
−65
0
-
MAX.
7.0
7.0
±100
V
DDD
1.1
150
70
tbf
UNIT
V
V
mV
V
W
°C
°C
V
May 1992
5
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