Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
FEATURES
•
Monolithic CMOS 3.3 V device with 5 V input stages
•
Digital PAL/NTSC/SECAM encoder
•
System pixel frequency 13.5 MHz
•
Accepts MPEG decoded data on 8-bit wide input port.
Input data format Cb, Y, Cr etc. “(CCIR
656)
” or
Y and Cb, Cr on 16 lines
•
Three DACs for CVBS, Y and C operating at 27 MHz
with 10 bit resolution
•
Three DACs for RGB operating at 27 MHz with 9 bit
resolution, RGB sync on CVBS and Y
•
Analog multiplexing between internal RGB and external
RGB on-chip
•
CVBS, Y, C and RGB output simultaneously
•
Closed captioning and teletext encoding including
sequencer and filter
•
Line 23 wide screen signalling encoding
•
On-chip Cr, Y, Cb to RGB dematrix, including gain
adjustment for Y and Cr, Cb, optionally to be by-passed
for Cr, Y, Cb output on RGB DACs
•
Fast I
2
C-bus control port (400 kHz)
•
Encoder can be master or slave
•
Programmable horizontal and vertical input
synchronization phase
•
Programmable horizontal sync output phase
•
Internal Colour Bar Generator (CBG)
•
Overlay with Look-Up Tables (LUTs) 8
×
3 bytes
•
Macrovision Pay-per-View copy protection system as
option, also used for RGB output.
SAA7182A; SAA7183A
This applies to SAA7183A only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Please contact your nearest Philips Semiconductor
sales office for more information
•
Controlled rise/fall times of output syncs and blanking
•
Down-mode of DACs
•
PQFP80 or PLCC84 package.
GENERAL DESCRIPTION
The SAA7182A; SAA7183A encodes digital YUV video
data to an NTSC, PAL, SECAM CVBS or S-Video signal
and also RGB.
Optionally, the YUV to RGB dematrix can be by-passed
providing the digital-to-analog converted Cb, Y, Cr signals
instead of RGB.
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data. It includes a sync/clock
generator and on-chip Digital-to-Analog Converters
(DACs).
The circuit is compatible to the DIG-TV2 chip family.
ORDERING INFORMATION
TYPE
NUMBER
SAA7182AWP;
SAA7183AWP
PACKAGE
NAME
PLCC84
QFP80
DESCRIPTION
plastic leaded chip carrier; 84 leads
plastic quad flat package; 80 leads (lead length 1.95 mm);
body 14
×
20
×
2.8 mm
VERSION
SOT189-2
SOT318-2
1996 Oct 02
2
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
QUICK REFERENCE DATA
SYMBOL
V
DDA3
V
DDD3
V
DDD5
I
DDA
I
DDD3
I
DDD5
V
i
V
o(p-p)
R
L
ILE
DLE
T
amb
PARAMETER
3.3 V analog supply voltage
3.3 V digital supply voltage
5 V digital supply voltage
analog supply current
3.3 V digital supply current
5 V digital supply current
input signal voltage levels
SAA7182A; SAA7183A
MIN.
3.1
3.0
4.75
−
−
−
TYP.
3.3
3.3
5.0
−
−
−
1.4
−
−
−
−
MAX.
3.5
3.6
5.25
110
80
10
−
300
±2
±1
+70
UNIT
V
V
V
mA
mA
mA
V
Ω
LSB
LSB
°C
TTL compatible
analog output signal voltages Y, C, CVBS and RGB without load
−
(peak-to-peak value)
load resistance
LF integral linearity error
LF differential linearity error
operating ambient temperature
75
−
−
0
1996 Oct 02
3
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