Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
CONTENTS
1
2
3
4
5
6
7
7.1
7.1.1
7.1.2
7.1.3
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.4
7.4.1
7.4.2
7.4.3
7.4.3.1
7.4.4
7.4.5
7.4.5.1
7.4.5.2
7.4.5.3
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.4.10.1
7.4.10.2
7.4.10.3
7.4.10.4
7.4.11
7.4.12
7.5
8
8.1
8.2
8.3
8.4
FEATURES
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Decoder part
Chrominance processor
Luminance processor
Synchronization
Expansion port (see Fig.2)
Monitor controls BCS (see Fig.2)
Brightness and contrast controls; see
Tables 1 and 2
Saturation control; see Table 3
RTCO output pin 44 (see Fig.11)
RTS1 and RTS0 outputs (pins 34 and 35)
Scaler part
Decimation filters
Vertical processing (VPU_Y)
RGB matrix
Anti-gamma ROM tables
Chrominance signal keyer
Scale control and vertical regions
Vertical bypass region
Vertical scaling region
Vertical regions (see Fig.12)
Output data representation and levels
Output FIFO register and VRAM port
VRAM port transfer procedures
Data burst transfer mode
Transparent data transfer mode
Interlaced processing
(OF bits, subaddress 20)
INCADR timing
Monochrome format (see Table 10)
VRAM port specifications
Field processing
Operation cycle
Power-on reset
PROGRAMMING MODEL
I
2
C-bus format
I
2
C-bus status information
Decoder part
Scaler part
9
10
11
12
12.1
13
14
14.1
14.2
14.3
14.4
15
16
17
LIMITING VALUES
CHARACTERISTICS
PROCESSING DELAYS
SAA7196
APPLICATION INFORMATION
Programming example
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
1996 Nov 04
2
Philips Semiconductors
Product specification
Digital video decoder, Scaler and Clock
generator circuit (DESCPro)
1
FEATURES
•
I
2
C-bus control
•
Only one crystal of 26.8 MHz required
•
Clock generator on chip.
2
GENERAL DESCRIPTION
SAA7196
•
Digital 8-bit luminance input [video (Y) or CVBS]
•
Digital 8-bit chrominance input [CVBS or C from CVBS,
Y/C, S-Video (S-VHS or Hi8)]
•
Luminance and chrominance signal processing for main
standards PAL, NTSC and SECAM
•
Horizontal and vertical sync detection for all standards
•
User programmable luminance peaking for aperture
correction
•
Compatible with memory-based features (line-locked
clock, square pixel)
•
Cross colour reduction by chrominance comb-filtering
for NTSC or special cross-colour cancellation for
SECAM
•
UV signal delay lines for PAL to correct chrominance
phase errors
•
Square-pixel format with 768/640 active samples per
line
•
The bidirectional expansion port (YUV-bus) supports
data rates of 780
×
f
H
(NTSC) and 944
×
f
H
(PAL,
SECAM) in 4 : 2 : 2 format
•
Brightness, contrast, hue and saturation controls for
scaled outputs
•
Down-scaling of video windows with 1023 active
samples per line and 1023 active lines per frame to
randomly sized windows
•
2D data processing for improved signal quality of scaled
luminance data, especially for compression applications
•
Chroma key (α-generation)
•
YUV to RGB conversation including anti-gamma
ROM tables for RGB
•
16-word output FIFO (32-bit words)
•
Output configurable for 32-, 24- and 16-bit
video data bus
•
Scaled 16-bit 4 : 2 : 2 YUV output
•
Scaled 15-bit RGB (5-5-5+α) and 24-bit (8-8-8+α)
output
•
Scaled 8-bit monochrome output
•
Line increment, field sequence (odd/even,
interlace/non-interlaced) and vertical reset control for
easy memory interfacing
•
Output of discontinuous data bursts of scaled video data
or continuous data output with corresponding qualifier
signals
•
Real-time status information
The CMOS circuit SAA7196, digital video decoder, scaler
and clock generator (DESCPro), is a highly integrated
circuit for DeskTop Video applications. It combines the
functions of a digital multistandard decoder (SAA7191B),
a digital video scaler (SAA7186) and a clock generator
(SAA7197).
The decoder is based on the principle of line-locked clock
decoding. It runs at square-pixel frequencies to achieve
correct aspect ratio. Monitor controls are provided to
ensure best display.
Four data ports are supported:
•
Port CVBS7 to CVBS0 of input interface; used in Y/C
mode (see Fig.1) to decode digitized luminance and
chrominance signals (digitized in two external ADCs).
In normal mode, only this input port is used and only one
ADC is necessary (see Fig.4)
•
Port CHR7 to CHR0 of input interface; used in Y/C
mode (see Fig.1) to decode digitized luminance and
chrominance signals (digitized in two external ADCs)
•
32-bit VRAM output port; interface to the video memory.
It outputs the down-scaled video data; different formats
and operation modes are supported by this circuit
•
16-bit expansion port; this is a bidirectional port.
In general, it establishes the digital YUV as known from
the SAA71x1 family of digital decoders. In addition, the
expansion port is configurable to send data from the
decoder unit or to accept external data for input into the
scaler. In input mode the clock rate and/or the sync
signals may be delivered by the external data source.
Decoder and scaler units can run at different clock rates.
The decoder processing always operates with a Line
Locked Clock (LLC). This clock is derived from the CVBS
signal and is suited best for memory based video
processing; the LLC clock is always present. The scaler
clock may be driven by the LLC clock or by an external
clock depending on the configuration of the expansion
port.
1996 Nov 04
3
Microchip MCU
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