INTEGRATED CIRCUITS
DATA SHEET
SAA7197
Clock Generator Circuit for desktop
video systems (CGC)
Product specification
File under Integrated Circuits, IC22
August 1996
Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
FEATURES
•
Suitable for Desktop Video systems
•
Two different sync sources selectable
•
PLL frequency multiplier to generate 4 times of input
frequency
•
Dividers to generate clocks LLCA, LLCB, LLC2A and
LLC2B (2nd and 4th multiples of input frequency)
•
PLL mode or VCO mode selectable
•
Reset control and power fail detection
QUICK REFERENCE DATA
SYMBOL
V
DDA
V
DDD
I
DDA
I
DDD
V
LFCO
f
i
V
I
V
O
T
amb
PARAMETER
analog supply voltage (pin 5)
digital supply voltage (pins 8, 17)
analog supply current
digital supply current
LFCO input voltage (peak-to-peak value)
input frequency range
input voltage LOW
input voltage HIGH
output voltage LOW
output voltage HIGH
operating ambient temperature range
MIN.
4.5
4.5
3
10
1
5.5
0
2.0
0
2.6
0
TYP.
5.0
5.0
−
−
−
−
−
−
−
−
−
GENERAL DESCRIPTION
SAA7197
The SAA7197 generates all clock signals required for a
digital TV system suitable for the SAA719x family. The
circuit operates in either the phase-locked loop mode
(PLL) or voltage controlled oscillator mode (VCO).
MAX.
5.5
5.5
9
60
V
DDA
8.0
0.8
V
DDD
0.6
V
DDD
70
V
V
UNIT
mA
mA
V
MHz
V
V
V
V
°C
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
SAA7197P
SAA7197T
PACKAGE
PINS
20
20
PIN POSITION
DIP
SO
MATERIAL
plastic
plastic
CODE
SOT146-1
SOT163-1
August 1996
2
Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
BLOCK DIAGRAM
SAA7197
handbook, full pagewidth
V
DDA
5
V
DDD1
V
DDD2
8
17
MS
1
SAA7197
LOOP
FILTER
MS = LOW
VCO
FREQUENCY
DIVIDER
1:2
FREQUENCY
DIVIDER
1:2
DELAY
PRE-FILTER
AND
PULSE
SHAPER
7
10
14
20
15
LLCA
LLCB
LLC2A
LLC2B
CREF
PHASE
DETECTOR
LFCO
11
POWER-ON
RESET
12
LFCO2 19
CE
2
16
LFCOSEL
PORD
V
SSA
V
SSD
3
4
6, 9, 13, 18
RESN
MEH461
Fig.1 Block diagram.
FUNCTION DESCRIPTION
The SAA7197 generates all clock signals required for a
digital TV system suitable for the SAA719x family
consisting of an 8-bit analog-to-digital converter (ADC8),
digital video multistandard decoder, square pixel
(DMSD-SQP), digital video colour space converter
(DCSC) and optional extensions. The SAA7197 completes
a system for Desktop Video applications in conjunction
with memory controllers.
The input signal LFCO is a digital-to-analog converted
signal provided by the DMDS-SQPs horizontal PLL. It is
the multiple of the line frequency:
7.38 MHz = 472
×
f
H
in 50 Hz systems
6.14 MHz = 360
×
f
H
in 60 Hz systems
LFCO2 (TTL-compatible signal from an external reference
source) can be applied to pin 19 (LFCOSEL = HIGH).
The input signal LFCO or LFCO2 is multiplied by factors 2
or 4 in the PLL (including phase detector, loop filter, VCO
and frequency divider) and output on LLCA (pin7), LLCB
(pin 10), LLC2A (pin 14) and LLC2B (pin 20). The
rectangular output signals have 50% duty factor. Outputs
with equal frequency may be connected together
externally. The clock outputs go HIGH during power-on
reset (and chip enable) to ensure that no output clock
signals are available the PLL has locked-on.
Mode select MS
The LFCO input signal is directly connected to the VCO at
MS = HIGH. The circuit operates as an oscillator and
frequency divider. This function is not tested.
August 1996
3
Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
Source select LFCOSEL
Line frequency control signal LFCO (pin 11) is selected by
LFCOSEL = LOW. LFCOSEL = HIGH selects LFCO2
input signal (pin 19). This function is not tested.
Chip enable CE
The buffer outputs are enabled and RESN set HIGH by
CE = HIGH (Fig.4). CE = LOW sets the clock outputs
HIGH and RESN output LOW.
CREF output
2 f
LFCO
output to control the clock dividers of the
DMSD-SQP chip family.
Power-on reset
SAA7197
Power-on reset is activated at power-on, when the supply
voltage decreases below 3.5 V (Fig.4) or when chip enable
is done. The indicator output RESN is LOW for a time
determined by capacitor on pin 3. The RESN signal can be
applied to reset other circuits of this digital TV system.
The LFCO or LFCO2 input signals have to be applied
before RESN becomes HIGH.
PINNING
SYMBOL
MS
CE
PORD
V
SSA
V
DDA
V
SSD1
LLCA
V
DDD1
V
SSD2
LLCB
LFCO
RESN
V
SSD3
LLC2A
CREF
LFCOSEL
V
DDD2
V
SSD4
LFCO2
LLC2B
Note
1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of
horizontal frequency.
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DESCRIPTION
mode select input (LOW = PLL mode)
(1)
chip enable /reset (HIGH = outputs enabled)
power-on reset delay, dependent on external
capacitor
PIN CONFIGURATION
halfpage
analog ground (0 V)
analog supply voltage (+5 V)
digital ground 1 (0 V)
line-locked clock output signal (4 times f
LFCO
)
digital supply voltage 1 (+5 V)
digital ground 2 (0 V)
line-locked clock output signal (4 times f
LFCO
)
line-locked frequency control input signal 1
reset output (active-LOW, Fig.4)
digital ground 3 (0 V)
line-locked clock output signal 2A (2 times f
LFCO
)
clock reference output, qualifier signal
(2 times f
LFCO
)
LFCO source select (LOW = LFCO selected)
(1)
digital supply voltage 2 (+5 V)
digital ground 4 (0 V)
line-locked frequency control input signal 2
(1)
line-locked clock output signal 2B (2 times f
LFCO
)
MS
CE
PORD
VSSA
VDDA
VSSD1
LLCA
VDDD1
VSSD2
1
2
3
4
5
20 LLC2B
19 LFCO2
18 VSSD4
17 VDDD2
16 LFCOSEL
SAA7197
6
7
8
9
15 CREF
14 LLC2A
13 VSSD3
12 RESIN
11 LFCO
MGL505
LLCB 10
Fig.2 Pin configuration.
August 1996
4
Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134);
ground pins as well as supply pins together connected.
SYMBOL
V
DDA
V
DDD
V
diff GND
V
O
P
tot
T
stg
T
amb
V
ESD
Note
PARAMETER
analog supply voltage (pin 5)
digital supply voltage (pins 8 and 17)
difference voltage V
DDA
−
V
DDD
output voltage (I
OM
= 20 mA)
total power dissipation (DIL20)
storage temperature range
operating ambient temperature range
electrostatic handling
(1)
for all pins
MIN.
−0.5
−0.5
−
−0.5
0
−65
0
−
SAA7197
MAX.
7.0
7.0
±100
V
DDD
1.1
150
70
tbf
V
V
UNIT
mV
V
W
°C
°C
V
1. Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
recommended to take normal handling precautions appropriate to
“Handling MOS devices”.
CHARACTERISTICS
V
DDA
= V
DDD
= 4.5 to 5.5 V; f
LFCO
= 5.5 to 8.0 MHz and T
amb
= 0 to 70
°C
unless otherwise specified.
SYMBOL
V
DDA
V
DDD
I
DDA
I
DDD
V
reset
V
11
V
i
f
LFCO
C
11
V
IL
V
IH
f
LFCO2
I
LI
C
I
V
OL
V
OH
t
d
PARAMETER
analog supply voltage (pin 5)
digital supply voltage (pins 8 and 17)
analog supply current (pin 5)
digital supply current (I
8
+ I
17
)
power-on reset threshold voltage
note 1
Fig.4
CONDITIONS
MIN.
4.5
4.5
3
10
−
TYP.
5.0
5.0
−
−
3.5
−
−
−
−
−
−
−
−
−
−
−
−
−
MAX.
5.5
5.5
9
60
-
UNIT
V
V
mA
mA
V
Input LFCO
(pin 11)
DC input voltage
input signal (peak-to-peak value)
input frequency range
input capacitance
0
1
5.5
−
V
DDA
V
DDA
8.0
10
V
V
MHz
pF
Inputs MS, CE, LFCOSEL and LFCO2
(pins 1, 2, 16 and 19); note 3
input voltage LOW
input voltage HIGH
input frequency range for LFCO2
input leakage current
input capacitance
LFCOSEL
others
Output RESN
(pin 12)
output voltage LOW
output voltage HIGH
RESN delay time
I
OL
= 2 mA
I
OH
=
−0.5
mA
C
3
= 0.1
µF;
Fig.4
0
2.4
20
0.4
V
DDD
200
V
V
ms
0
2.0
5.5
50
−
−
0.8
V
DDD
8.0
150
10
5
V
V
MHz
µA
µA
pF
August 1996
5
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