INTEGRATED CIRCUITS
DATA SHEET
SAA7201
Integrated MPEG2 AVG decoder
Objective specification
File under Integrated Circuits, IC02
1997 Jan 29
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
FEATURES
General
•
Uses single external Synchronous DRAM (SDRAM)
organized as 1M
×
16 interfacing at 81 MHz; compatible
with the SDRAM ‘lite’ or ‘PC’
•
Fast external CPU interface; 16-bit data + 8-bit address
•
Dedicated input for audio and video data in PES or ES
format; data input rate:
≤9
Mbytes/s in byte mode;
≤20
Mbit/s in bit serial mode; audio and/or video data
can also serve as input via CPU interface
•
Single 27 MHz external clock for time base reference
and internal processing; all required decoding and
presentation clocks are generated internally
•
Internal system time base at 90 kHz can be
synchronized via CPU port
•
Flexible memory allocation under control of the external
CPU enables optimized partitioning of memory for
different tasks
•
Boundary scan (JTAG) plus external SDRAM self test
implemented
•
Supply voltage 3.3 V
•
Package 160 QFP.
CPU relation
•
16-bit data, 8-bit address, or 16-bit multiplexed bus;
Motorola and Intel mode supported
•
Support for fast DMA transfer to either internal registers
or external SDRAM
•
Maximum sustained rate to the external SDRAM is
9 Mbytes/s.
MPEG2 system
•
Parsing of MPEG2 PES and MPEG1 packet streams
•
Double System Time Clock (STC) counters for
discontinuity handling
•
Time stamps or CPU controlled audio/video
synchronization
•
Support for seamless time base change (edition)
•
Processing of errors flagged by channel decoding or
demux section
•
Support for retrieval of PES header and PES private
data.
MPEG2 audio
SAA7201
•
Decoding of 2 channel, layer I and II MPEG audio;
support for mono, stereo, intensity stereo and dual
channel mode
•
Constant and variable bit rates up to 448 kbit/s
•
Audio sampling frequencies: 48, 44.1, 32, 24, 22.05 and
16 kHz
•
CRC error detection
•
Selectable output channel in dual channel mode
•
Independent volume control for both channels and
programmable inter-channel crosstalk control through a
baseband audio processing unit
•
Storage ancillary data up to 54 bytes
•
Dynamic range control at output
•
Muting possibility via external controller; automatic
muting in case of errors
•
Generation of ‘beeps’ with programmable tone height,
duration and amplitude
•
Serial two channel digital audio output with 16, 18, 20 or
22 bits per sample, compatible with either I
2
S or
Japanese formats
•
Serial SPDIF audio output
•
Clock output 256 or 384
×
f
s
for external D/A converter
•
Audio input buffer in external SDRAM with
programmable size (default is 64 kbit)
•
Programmable processing delay compensation
•
Software controlled stop, pause, restricted skip, and
restart functions.
MPEG2 video
•
Decoding of MPEG2 video up to main level, main profile
•
Nominal video input buffer size equals 2.6 Mbit for Video
Main Profile and Main Level (MP@ML)
•
Output picture format: CCIR-601 4 : 2 : 2 interlaced
pictures; picture format 720
×
576 at 50 Hz or 720
×
480
at 60 Hz
•
3 : 2 pull-down supported with 24 and 30 Hz sequences
•
Support of constant and variable bit rates up to 15 Mbit/s
•
Output interface at 8-bit wide, 27 MHz UYVY
multiplexed bus
•
Horizontal and vertical pan and scan allows the
extraction of a window from the coded picture
1997 Jan 29
2
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
•
Flexible horizontal continuous scaling from 0.5 up to 4
allows easy aspect ratio conversion including support
for 2.21 : 1 aspect ratio movies
•
Vertical scaling with fixed factors 0.5, 1 or 2 to support
picture scaling and up-sampling
•
Scaling of incoming pictures to 25% of their original size
with anti-aliasing filtering to free screen space for
graphics applications like electronic program guides
•
Non-full screen MPEG pictures will be displayed in a box
of which position and background colour are adjustable
by the external CPU
•
Video output may be slaved to internally (master)
generated or externally (slave) supplied HV
synchronization signals; the position of active video is
programmable; MPEG timebase changes do not
affected the display phase
•
Video output direct connectable to SAA718X encoder
family
•
Various trick modes under control of external CPU:
– Freeze I or P pictures; restart on I picture
– Freeze on B pictures; restart at any moment
– Scanning and decoding of I or I and P pictures
– Single step mode
– Repeat/Skip field for time base correction.
Graphics
•
Graphics is region based and presented in boxes
independent of video format
•
Screen arrangement of boxes is determined by display
list mechanism which allows for multiple boxes,
background loading, fast switching, scrolling and fading
of regions
SAA7201
•
Support of 2, 4, 8 bits/pixel bit-maps in fixed bit-maps or
coded in accordance to the DVB variable/run length
standard for region bases graphics
•
Optimized memory control in MPEG video decoding
allows for storage of graphical bit-maps up to 1.2 Mbit in
50 Hz and 2.0 Mbit in 60 Hz systems
•
VL/RL encoding enables full screen graphics at
8 bit/pixel in 50 Hz
•
Fast CPU access enables full bit-map updates within a
display field period
•
Display colours are obtained via colour look-up tables;
CLUT output is YUVT at 8-bit for each signal component
thus enabling 16M different colours and 6-bit for T
(transparency) which gives 64 mixing levels with video
•
Bit-map table mechanism to specify a sub-set of entries
if the CLUT is larger than required by the coded bit
pattern; supported bit-map tables are 16 to 256,
4 to 256 and 4 to 16
•
Graphics boxes may not overlap vertically; if 256 entry
CLUT has to be down loaded, a vertical separation of
1 field line is mandatory
•
Internal support for fast block moves in the external
SDRAM during MPEG decoding
•
Graphics mechanism can be used for signal generation
in the vertical blanking interval; useful for teletext, wide
screen signalling, closed caption etc.
•
Support for a single down-loadable cursor of 1 kpixel
with programmable shape; supported shapes are
8
×
128, 16
×
64, 32
×
32, 64
×
16 and 128
×
8
•
Cursor colours are determined via a 4-entry CLUT with
YUVT at 6, 4, 4 respectively 2 bits; mixing of cursor with
video + graphics in 4 levels
•
Cursor can be moved freely across the screen without
overlapping restrictions.
1997 Jan 29
3
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
GENERAL DESCRIPTION
The SAA7201 is an MPEG2 decoder which combines
audio decoding and video decoding. Additionally to these
basic MPEG functions it also provides means for
enhanced graphics and/or on-screen display.
QUICK REFERENCE DATA
SYMBOL
V
DD
V
CC
I
DD(tot)
f
CLK
∆f
CLK
PARAMETER
functional supply voltage
pad supply voltage
total supply current at V
DD
= 3.3 V
clock frequency
frequency deviation
MIN.
3.0
3.0
−
−
3.3
3.3
tbf
27.0
TYP.
SAA7201
Due to an optimized architecture for audio and video
decoding, maximum capacity in the external memory and
processing power from the external CPU is available for
the support for graphics.
MAX.
3.6
3.6
−
−
+30
×
10
−6
V
V
UNIT
mA
MHz
−30 ×
10
−6
−
ORDERING INFORMATION
TYPE
NUMBER
SAA7201H
PACKAGE
NAME
QFP160
DESCRIPTION
plastic quad flat package; 160 leads (lead length 1.95 mm);
body 28
×
28
×
3.4 mm; high stand-off height
VERSION
SOT322-4
1997 Jan 29
4
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
BLOCK DIAGRAM
SAA7201
handbook, full pagewidth
VDDCO1 to
VDDCO4
SDRAM_WE
SDRAM_CAS
SDRAM_UDQ
SDRAM_DATA
(15 to 0)
READI
CP81MEXT
READO
83
81
80
16
VDDA
VDD1 to
VDD16
121
SDRAM_RAS
77
4
75
74
SDRAM_ADDR
(11 to 0)
78
12
MEMORY
INTERFACE
CP81M
16
84
A_STROBE
V_STROBE
AV_DATA(0 to 7)
ERROR
159
148
8
147
AUDIO/VIDEO
INTERFACE
VIDEO INPUT
BUFFER & SYNC
VIDEO
DECODER
SYSTEM TIME
BASE UNIT
CPU_TYPE
MUX
CS
DS
AS
R/W
DTACK
ADDRESS(8 to 1)
DATA(15 to 0)
IRQ(3 to 0)
DMA_REQ
DMA_ACK
DMA_RDY
DMA_DONE
CLK
RESET
4
4
3
6
5
124
138
CLOCK
GENERATION
AUDIO INPUT
BUFFER & SYNC
16
122
MGD322
2
1
8
9
10
11
12
8
16
HOST
INTERFACE
SAA7201
106
DISPLAY
UNIT
107
HS
VS
8
GRAPHICS
UNIT
YUV(7 to 0)
119
143
142
145
146
139
GRPH
SD
SCLK
WS
SPDIF
FSCLK
AUDIO
DECODER
JTAG
4
VSSCO1 to VSSCO4
VSS1 to VSS16
VSSA
Fig.1 Block diagram.
1997 Jan 29
5
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