INTEGRATED CIRCUITS
DATA SHEET
SAA7219
MPEG2 Transport RISC processor
Preliminary specification
File under Integrated Circuits, IC02
1999 Sep 20
Philips Semiconductors
Preliminary specification
MPEG2 Transport RISC processor
CONTENTS
1
1.1
1.2
1.3
2
2.1
2.2
3
4
5
5.1
5.2
6
6.1
7
8
8.1
8.2
8.3
8.4
8.5
9
10
11
FEATURES
External interfaces
CPU related features
MPEG-2 systems features
GENERAL DESCRIPTION
SAA7219 overview
SAA7219 in a DVB system
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING INFORMATION
Pinning
Pin description
APPLICATION INFORMATION
Memory configurations
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
SAA7219
1999 Sep 20
2
Philips Semiconductors
Preliminary specification
MPEG2 Transport RISC processor
1
FEATURES
SAA7219
•
Conditional access descrambling Digital Video
Broadcasting (DVB) compliant and MULTI2 compliant
•
Stream demultiplexing: Transport Stream (TS),
Packetized Elementary Stream (PES), program and
proprietary streams
•
Internal 32-bit MIPS RISC based Central Processing
Unit (CPU) supporting MIPS16 instruction set and
running at 81 MHz
•
Low-power sleep modes supported across the chip
•
Comprehensive driver software and development tool
support
•
Package: SQFP208.
1.1
External interfaces
•
A General Purpose/High Speed (GP/HS) interface
supporting stream recording through IEEE 1394
interface IC
•
An extended JTAG interface for board test support.
1.2
CPU related features
The SAA7219 contains an embedded RISC CPU, which
incorporates the following features:
•
A 32-bit PR3930 core running at 81 MHz
•
8-kbyte, 2-way set associative instruction cache
•
4-kbyte, 4-way set associative data cache
•
A programmable Low-power mode, including wake-up
on interrupt
•
A memory management unit with 32 odd/even entries
and variable page sizes
•
Multiply/accumulate/divide unit with fast
multiply/accumulate for 16-bit and 32-bit operands
•
Two fully independent 24-bit timers and one 24-bit timer
including watchdog facilities
•
A real-time clock unit (active in Sleep mode)
•
Built-in software debug support unit as part of Extended
Enhanced JTAG debug interface
•
On-chip SRAM of 4 kbytes for storing code which needs
fast execution.
1.3
MPEG-2 systems features
•
Versatile compressed stream input at 108 Mbits/s
•
A 32-bit microcontroller extension bus supporting
DRAM, SDRAM, Flash, (E)PROM and external memory
mapped I/O devices. It also supports a synchronous
interface to communicate with the integrated MPEG
Audio Video Graphics Decoder (AVGD) SAA7215 at
40.5 Mbytes.
•
An IEEE 1284 interface (Centronics) supporting master
and slave modes. Usable as a general purpose port.
•
An interface to IEEE 1394 devices (such as Philips
PDI 1394 chip-set)
•
Two UART (RS232) data ports with Direct Memory
Access (DMA) capabilities (187.5 kbits/s) including
hardware flow control signals RXD, TXD, RTS and CTS
for modem support
•
A Synchronous Serial Interface (SSI) to connect an
off-chip modem analog front-end
•
An elementary UART with DMA capabilities, dedicated
to front panel devices for instance
•
Two dedicated smart-card reader interfaces (ISO 7816
compatible) with DMA capabilities
•
Two I
2
C-bus master/slave transceivers with DMA
capabilities, supporting the standard (100 kbit/s) and
fast (400 kbits/s) I
2
C-bus modes
•
32 general purpose, bidirectional I/O interface pins, 8 of
which may also be used as interrupt inputs
•
One Pulse Width Modulated (PWM) output with 8-bit
resolution
•
Hardware based parsing of Transport Stream (TS),
Philips Semiconductors program and proprietary
software data streams. Maximum input rate is
108 Mbits/s.
•
A real-time descrambler consisting of 3 modules:
– A control word bank containing 14 pairs (odd, even)
of control words and a default control word
– The DVB descrambler core implementing the stream
decipher and block decipher algorithms
– The MULTI2 descrambler algorithm implementing
the CBC and OFB mode descrambling functions.
1999 Sep 20
3
Philips Semiconductors
Preliminary specification
MPEG2 Transport RISC processor
•
Hardware section filtering based on 32 different Packet
Identifiers (PIDs) with a flexible number of filter
conditions (8 or 4-byte condition plus 8 or 4-byte mask)
per PID and a total filter capacity of 40 (8-byte condition
checks) or up to 80 (4-byte condition checks) filter
conditions:
– 4 TS/PES filters for retrieval for data at TS or PES
level for applications such as subtitling, TXT or
retrieval of private data
– Flexible DMA based storage of the 32 section
substreams and 4 TS/PES data substreams in the
external memory
•
System time base management with a double counter
mechanism for clock control and discontinuity handling,
2 Presentation Time Stamp (PTS)/Decoding Time
Stamp (DTS) timers
•
A GP/HS filter which can serve as an alternate input
from for example IEEE 1394 devices. The IEEE 1394
GP/HS mode supports packet insertion and has an
internal SRAM for storing 2 packets. It can also output
either scrambled or descrambled TS to IEEE 1394
devices.
2
2.1
GENERAL DESCRIPTION
SAA7219 overview
2.2
SAA7219 in a DVB system
SAA7219
The SAA7219 receives transport streams through a
versatile stream input interface capable of handling both
byte-parallel and bit-serial streams in various formats,
supporting data streams up to and including 13.5 Mbyte/s
(108 Mbits/s). The stream data is first applied to an on-chip
descrambler incorporating a DVB descrambling algorithm,
on the basis of 14 control word pairs stored in on-chip
RAM. Demultiplexing is subsequently applied to the
stream, to separate up to 32 individual data streams.
The demultiplexer section includes clock recovery and
timebase management. Program Specific Information
(PSI), Service Information (SI), Conditional Access (CA)
messages and private data are selected and stored in
external memory, for subsequent off-line processing by
the internal PR3930 CPU core.
To support advanced board testing facilities the SAA7219
includes boundary scan test hardware, according to the
EJTAG standard. The device features a Low-power sleep
mode, which is capable of sustaining set-top box stand-by
functionality, thus eliminating the need for a separate
front-panel controller. The SAA7219 requires a supply
voltage of 3.3 V and most devices input and output
interfaces are 5 V tolerant except the extension bus which
is 3.3 V only. The SAA7219 is mounted in a SQFP208
package.
The device is part of a comprehensive source decoding kit
which contains all the hardware and software required to
receive and decode MPEG-2 transport streams, including
descrambling, demultiplexing. In addition, it includes a
PR3930 core which is a 32-bit MIPS RISC-based CPU
core supporting the MIPS 16 instruction set to reduce
memory requirements and several peripheral interfaces
such as UARTs, I
2
C-bus units, an IEC 1883, and an
IEEE 1284 (Centronics) interface. The SAA7219 is
therefore capable of performing all controller tasks in
digital television receiver applications such as set-top
boxes. Furthermore, the SAA7219 is compliant to DVB
and MULTI2 standards.
The SAA7219 has been designed to offer optimum
performance when used with the SAA7215 for MPEG-2e
AVG decoding.
•
Synchronous bus interface transfer at 40.5 MHz on
16 bits
•
SAA7215 has one dedicated SDRAM for MPEG-2e
audio video handling and one for graphics and CPU
data. The second memory offers high bandwidth and
low latency to the SAA7219 when accessing it to
download graphics or executing some applications. This
enables a high level of performance together with a low
system cost by having one SDRAM for graphics and
CPU data.
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA7219HS
DESCRIPTION
VERSION
SOT316-1
SQFP208 plastic shrink quad flat package; 208 leads (lead length 1.3 mm);
body 28
×
28
×
3.4 mm
1999 Sep 20
4
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1999 Sep 20
input
stream
output
stream
PWM
demultiplexer descrambler section
CPU section
Philips Semiconductors
BLOCK DIAGRAM
MIPS
PR3930
CORE
INPUT
INTERFACE
DESCRAMBLER
DVB AND MULTI2
MPEG system-bus
AV
FILTER
AVD
interface
AUDIO AND
VIDEO
INTERFACE
PID
FILTER
DATA CACHE
INSTRUCTION CACHE
GP/HS
INTERFACE
1394 GATEWAY
PCR
PROCESSING
SECTION
FILTERS
TS/PES
FILTERS
TIMER 1
TIMER 2
FILTER DMA
CONTROLLER
MPEG SYSTEM
GATEWAY
M
MPEG SYSTEM
INT.HANDLER
Reset
Clock
PI-bus
MPEG2 Transport RISC processor
TIMER 3 (WATCHDOG)
DSU
MMU
EJTAG
5
M
M
SSI
0
1
1284
PIO
INTERFACE
I
2
C
RTC
32 KHz
M
S
UART
2 0 1
M
S
S
S
INTERRUPT
CONTROLLER
S
4-KBYTE
SRAM
1
peripheral section
FCE374
S
S
PI-BUS
CTRL
EXTENSION BUS
CONTROLLER
CARD READER
0
JTAG
JTAG interface
UART and SSI
connections
external
bus interface
32-bit PIO
smart card
interface
SCL and 1284 bus
SDA lines
M = master peripheral with embedded DMA channel
S = slave peripheral
Preliminary specification
SAA7219
Fig.1 Block diagram.
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