Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
FEATURES
•
Compatibility with CD-I, CD-ROM, MPEG-video
DVD-ROM and DVD-video applications
•
Designed for very high playback speeds
•
Typical CD-ROM operation up to n = 12, DVD-ROM to
n = 1.9, maximum rates (tbf)
•
Matched filtering, quad-pass error correction
(C1-C2-C1-C2), overspeed audio playback function
included (up to 3 kbytes buffer)
•
Lock-to-disc playback, Constant Angular Velocity
(CAV), pseudo-Constant Linear Velocity (CLV) and CLV
motor control loops
•
Interface to 32 kbytes SRAM for DVD error correction
and de-interleave
•
Sub-code/ header processing for DVD and CD formats
•
Programmable HF equalizer
•
In DVD mode it is still compatible with Philips block
decoders
•
Sub-CPU interface can be parallel or fast I
2
C-bus
•
On-chip clock multiplier.
GENERAL DESCRIPTION
This device is a high-end combined Compact Disc (CD)
and Digital Versatile Disc (DVD) compatible decoding
device. The device operates with an external 32 kbytes
S-RAM memory for de-interleaving operations. The device
provides quad-pass error correction for CD-ROM
applications (C1-C2-C1-C2) and operates in lock-to-disk,
CAV, pseudo CLV and CLV modes.
QUICK REFERENCE DATA
SYMBOL
V
DDD
I
DDD
V
DDA
I
DDA
f
xtal
T
amb
T
stg
PARAMETER
digital supply voltage
digital supply current
analog supply voltage
analog supply current
crystal input frequency
operating ambient temperature
storage temperature
−
4.5
−
4
−20
−55
MIN.
4.5
70
5.0
70
25
−
−
TYP.
5.0
SAA7335
In DVD modes double-pass C1-C2 error correction is used
which is capable of correcting up to 5 C1 frame errors and
16 C2 frame errors.
The SAA7335 contains all the functions required to
decode an EFM or EFM+ HF signal directly from the laser
pre-amplifier, including analog front-end, PLL data
recovery, demodulation and error correction. The spindle
motor interface provides both motor control signals from
the demodulator and, in addition, contains a tachometer
loop that accepts tachometer pulses from the motor unit.
The SAA7335 has two independent microcontroller
interfaces. The first is a serial I
2
C-bus and the second is a
standard 8-bit multiplexed parallel interface. Both of these
interfaces provide access to a total of 32
×
8-bit registers
for control and status.
This data sheet contains an descriptive overview of the
device together with electrical and timing characteristics.
For a detailed description of the device refer to the user
guide
“SAU/UM96018”.
Supply of this CD/DVD IC does not convey an implied
license under any patent right to use this IC in any CD or
DVD application.
MAX.
5.5
300
5.5
300
tbf
+70
+125
V
UNIT
mA
V
mA
MHz
°C
°C
1997 Aug 11
2
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
PINNING
SYMBOL
V
SSA1
I
ref
REFLo
REFHi
VREF
HFIN
V
SSA2
AGCOUT
V
DDA2
V
DDD1
V
SSD1
OTD
MOTO1
n.c.
MOTO2/T3
n.c.
T1
T2
V
DDD2
V
SSD2
TEST1
TEST2
POR
MUXSWICH
n.c.
CL1
BCAIN
SDA
SCL
INT
V
DDD3
V
SSD3
da7
da6
da5
n.c.
da4
n.c.
da3
da2
1997 Aug 11
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TYPE
supply
I
I
I
I
I
supply
O
supply
supply
supply
I
O
−
I/O
−
I
I
supply
supply
I
I
I
I
−
O
I
I/O
I
O
supply
supply
I/O
I/O
I/O
−
I/O
−
I/O
I/O
analog ground 1
analog current reference input for ADC
analog low reference input for ADC
analog high reference input for ADC
analog negative input
analog positive input
analog ground 2
analog test pin output
analog supply voltage 2
digital supply voltage 1
digital ground 1
off track detect input
3-state motor control output
not connected, reserved
motor control output/tachometer 3 input
not connected, reserved
tachometer 1 input
tachometer 2 input
digital supply voltage 2
digital ground 2
test input 1
test input 2
power-on reset input
use clock multiplier input
not connected, reserved
divided clock output
BCA input
sub-CPU I
2
C-bus serial data input/output
sub-CPU I
2
C-bus serial clock input
sub-CPU interrupt output (open-drain)
digital supply voltage 3
digital ground 3
sub-CPU data bus bit 7 input/output (parallel)
sub-CPU data bus bit 6 input/output (parallel)
sub-CPU data bus bit 5 input/output (parallel)
not connected, reserved
sub-CPU data bus bit 4 input/output (parallel)
not connected, reserved
sub-CPU data bus bit 3 input/output (parallel)
sub-CPU data bus bit 2 input/output (parallel)
4
DESCRIPTION
SAA7335
Philips Semiconductors
Preliminary specification
DSP for CD and DVD-ROM systems
SAA7335
SYMBOL
da1
n.c.
da0
V
DDD4
V
SSD4
WRi
RDi
ALE
CSi
STOPCLOCK
n.c.
V4
EBUOUT
SYNC
FLAG
DATA
BCLK
WCLK
V
DDD5
V
SSD5
RAMRW
n.c.
RAMDA7
RAMDA6
RAMDA5
RAMDA4
RAMDA3
RAMDA2
n.c.
RAMDA1
RAMDA0
V
DDD6
V
SSD6
RAMAD0
RAMAD1
RAMAD2
RAMAD3
RAMAD4
RAMAD5
RAMAD6
V
DDD7
1997 Aug 11
PIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
TYPE
I/O
−
I/O
supply
supply
I
I
I
I
O
−
O
O
O
O
O
I/O
I/O
supply
supply
O
−
I/O
I/O
I/O
I/O
I/O
I/O
−
I/O
I/O
supply
supply
O
O
O
O
O
O
O
supply
not connected, reserved
DESCRIPTION
sub-CPU data bus bit 1 input/output (parallel)
sub-CPU data bus bit 0 input/output (parallel)
digital supply voltage 4
digital ground 4
sub-CPU write enable input (active LOW)
sub-CPU read enable input (active LOW)
sub-CPU address latch enable input
sub-CPU chip select input (active HIGH)
stop clock output
not connected, reserved
serial subcode output (for CD)
digital audio output
I
2
S-bus sector sync output
I
2
S-bus correction flag output
I
2
S-bus serial data output
I
2
S-bus bit serial clock input/output
I
2
S-bus word clock input/output
digital supply voltage 5
digital ground 5
RAM read/write control output
not connected, reserved
RAM data bus bit 7 input/output
RAM data bus bit 6 input/output
RAM data bus bit 5 input/output
RAM data bus bit 4 input/output
RAM data bus bit 3 input/output
RAM data bus bit 2 input/output
not connected, reserved
RAM data bus bit 1 input/output
RAM data bus bit 0 input/output
digital supply voltage 6
digital ground 6
RAM address bit 0 output
RAM address bit 1 output
RAM address bit 2 output
RAM address bit 3 output
RAM address bit 4 output
RAM address bit 5 output
RAM address bit 6 output
digital supply voltage 7
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
