INTEGRATED CIRCUITS
DATA SHEET
SAA7382
Error correction and host interface
IC for CD-ROM (ELM)
Preliminary specification
File under Integrated Circuits, IC01
1996 Apr 25
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
CONTENTS
1
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
.10
8
9
10
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
12
13
14
15
FEATURES
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
CD-DSP interface and data input
Error correction and EDC check
Host interface
Subcode channel Q-to-W buffering
External buffer memory
Sub-CPU registers
Register Descriptions
Sub-CPU interface
Host registers
CD-DSP Timings
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
TIMING CHARACTERISTICS
Q-to-W subcode interface timing
External memory SRAM timing
External memory DRAM timing
Sub-CPU interface timing
ATAPI host interface timing
SANYO compatibility mode host interface
timing
Oak compatibility mode host interface timing
Crystal oscillator
PACKAGE OUTLINE
SOLDERING
DEFINITIONS
LIFE SUPPORT APPLICATIONS
SAA7382
1996 Apr 25
2
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
1
FEATURES
2
GENERAL DESCRIPTION
SAA7382
•
CD-ROM (Mode 1) and CD-I (Mode 2 - Form 1 and
Form 2) formats supported
•
Real-time error detection and correction in hardware
•
Suitable for double speed, n = 2.
•
Maximum host transfer burst rate of 8.3 Mbyte/s
•
Corrects two errors per symbol with erasure correction
•
36 kbit of on-chip error correction buffer RAM
•
12-byte command FIFO and 12-byte status FIFO
•
Compatible with the Advanced Technology Attachment
(ATA) register set and the Advanced Technology
Attachment Program Interface (ATAPI) command set
•
Operates with popular memories. (up to 128 kbyte
SRAM; 1 to 16 Mbit DRAM, different speed grades,
nibble or byte wide)
•
Interface to Integrated Drive Electronics (IDE) bus
without external bus drivers
•
Q-to-W subcode buffering, de-interleaving and
correction are supported
•
Device can operate with audio RAMs. A RAM test allows
bad segments to be identified.
3
QUICK REFERENCE DATA
SYMBOL
V
DDD1
V
DDD2
I
DDD
f
clk
T
amb
T
stg
4
PARAMETER
digital supply voltage 1
digital supply voltage 2
supply current
clock frequency
operating ambient temperature
storage temperature
The SAA7382 decoder is a block decoder buffer manager
for high-speed CD-ROM applications that integrates
real-time error correction and detection and host interface
data transfer functions into a single chip.
The SAA7382 has an on-chip 36-kbit memory. This
memory is used as a buffer memory for error and erasure
corrections. The chip also has a buffer memory interface
thus enabling the connection of SRAM up to 128 kbytes, or
DRAM up to 16 Mbits. The on-chip memory is sufficient to
buffer 1 sector of data. The external memory can buffer
many more, depending on memory size.
The error corrector of the SAA7382 can perform 2-pass
error correction in real-time. Buffer memory for this
correction is integrated on-chip.
The SAA7382 has an host interface that is compatible with
the SANYO LC89510 or OAK OTI-012 and also
compatible with the ATA/IDE/ATAPI hard disc interface
bus. (All ATAPI registers are present in hardware).
Supply of this Compact Disc IC does not convey an implied
license under any patent right to use this IC in any
Compact Disc application.
MIN.
3.0
4.5
−
15.2
0
−55
5
TYP.
3.3
60
−
−
MAX.
3.6
5.5
−
+70
+125
V
V
UNIT
mA
MHz
°C
°C
16.9344 18.0
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA738
2
GP
QFP80
DESCRIPTION
plastic quad flat package; 80 leads; lead length 1.95 mm;
body 14
×
20
×
2.8 mm
VERSION
SOT318-2
1996 Apr 25
3
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
5
BLOCK DIAGRAM
SAA7382
handbook, full pagewidth
RCK
DGND
VDDD2
50, 74
SFSY
28
SUB
29
BCK
WS
31
DATA
C2PO
34
35
TEST2
23
TEST1
25
1, 14, 24,
41, 59, 68
32
30
33
VDDD1
DECODER
SERIAL
INTERFACE
TEST
SDA
SCL
INT
RESET
SYN
36
75-80
37
38
39
40
MICRO-
CONTROLLER
INTERFACE
ERROR
CORRECTOR
RA0 to RA5
SAA7382
MEMORY
MANAGER
2-10
RA6 to RA14
12
11
13
15-22
RA16/CAS
RA15/RAS
RWE
RD0 to RD7
SRAM
CACHE
DMACK
DA1
DA2/EJECT
CS2/SELRQ
IOCS16
45
70
71
72
73
OSCILLATOR
HOST INTERFACE
27
26
CRIN
CROUT
42
CS1/HEN
43
44
69
46
47
48
49
51-58
60-67
MGD308
HRD
DMARQ/DTEN
SCRST/STEN
HWR DA0/CMD
HD0 to HD7 HD8 to HD15
IRQ/EOP/HFBC
IORDY/WAIT/HFBLB
Fig.1 Block diagram.
1996 Apr 25
4
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
6
PINNING
SYMBOL
DGND1
RA6
RA7
RA8
RA9
RA10
RA11
RA12
RA13
RA14
RA15/RAS
RA16/CAS
RWE
DGND2
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
TEST2
DGND3
TEST1
CROUT
CRIN
SFSY
RCK
SUB
BCK
V
DDD1
WS
DATA
C2PO
SDA
SCL
INT
RESET
SYN
1996 Apr 25
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
−
O
O
O
O
O
O
O
O
O
O
O
O
−
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
−
I
O
I
I
O
I
I
−
I
I
I
I/O
I
O
I
I
digital ground 1
buffer RAM address bus output line 6
buffer RAM address bus output line 7
buffer RAM address bus output line 8
buffer RAM address bus output line 9
buffer RAM address bus output line 10
buffer RAM address bus output line 11 (SRAM) only
buffer RAM address bus output line 12 (SRAM) only
buffer RAM address bus output line 13 (SRAM) only
buffer RAM address bus output line 14 (SRAM) only
DESCRIPTION
SAA7382
buffer RAM address bus output line 15 (SRAM) or RAS (DRAM)
buffer RAM address bus output line 16 (SRAM) or CAS (DRAM)
buffer RAM write enable output
digital ground 2
buffer RAM data bus bidirectional line 0
buffer RAM data bus bidirectional line 1
buffer RAM data bus bidirectional line 2
buffer RAM data bus bidirectional line 3
buffer RAM data bus bidirectional line 4
buffer RAM data bus bidirectional line 5
buffer RAM data bus bidirectional line 6
buffer RAM data bus bidirectional line 7
test input 2
digital ground 3
test input 1
clock oscillator output
clock oscillator input
serial subcode input frame sync input
serial subcode clock output (active LOW)
serial input for Q-to-W subcode input
serial interface bit clock input
digital supply voltage 1 (3.3 V)
serial interface word clock input
serial data input
serial interface flag input
sub-CPU serial data input/output
sub-CPU serial clock input
sub-CPU open-collector interrupt output
power-on reset input (active LOW)
sync signal input from sub-CPU
5
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