INTEGRATED CIRCUITS
DATA SHEET
SAA7385
Error correction and host interface
IC for CD-ROM (SEQUOIA)
Preliminary specification
File under Integrated Circuits, IC01
1996 Jun 19
Philips Semiconductors
Preliminary specification
Error correction and host interface IC
for CD-ROM (SEQUOIA)
CONTENTS
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2
3
4
5
6
7
7.1
7.2
7.3
7.4
8
8.1
8.2
8.3
8.4
9
9.1
9.2
10
10.1
10.2
FEATURES
General
53CF94 SCSI controller
80C32 high-speed microcontroller
Front-end interface logic
Buffer controller
Hardware third-level error correction
Additional product support
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
80C32 microcontroller
53CF94 fast SCSI controller
Input clock doubler
Front-end
MICROCONTROLLER INTERFACE
Microcontroller interface status register
Microcontroller interface command register
Microcontroller interrupts
Microcontroller RAM organization
FRONT PANEL AND MISCELLANEOUS
CONTROL SIGNALS
S2B UART registers
Miscellaneous control registers
FRONT-END
Minute Second Frame (MSF) addressing and
header information
Front-end status and control
11
11.1
11.2
11.3
11.4
11.5
11.6
12
13
14
15
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
16
17
17.1
17.2
17.3
17.4
18
19
BUFFER MANAGER
SAA7385
Front-end to buffer manager interface
Microcontroller to buffer manager interface
ECC to buffer manager interface
SCSI to buffer manager interface
Miscellaneous buffer manager considerations
53CF94 related registers
FRAME BUFFER ORGANIZATION
SUMMARY OF CONTROL REGISTER MAP
LIMITING VALUES
OPERATING CHARACTERISTICS
I
2
S-bus timing; data mode
EIAJ timing; audio mode
R-W timing (see Fig.15)
C-flag timing (see Fig.16)
S2B interface timing
SCSI interface timing
Microprocessor interface
DRAM interface (the SAA7385 is designed to
operate with standard 70 ns DRAMs)
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
1996 Jun 19
2
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
1
1.1
FEATURES
General
1.5
Buffer controller
SAA7385
•
Ten level arbitration logic
•
Utilizes low cost 70 ns DRAMs
•
Page mode DRAM access for high-speed error
correction and SCSI data transfer
•
Data organization by 3 kbyte frames
•
256 kbyte or 1 Mbyte DRAM supported.
1.6
Hardware third-level error correction
•
Single chip digital solution for an 8
×
speed CD-ROM
controller chip
•
10 Mbytes/s NCR53CF94 equivalent SCSI controller
included
•
High-speed 80C32 microcontroller with 256
×
8
scratch-pad SRAM included
•
High performance CD-ROM interface logic
•
128 pin QFP package.
1.2
53CF94 SCSI controller
•
Third-level correction provides superior performance in
unfavourable conditions
•
Full hardware error correction to reduce microcontroller
overhead
•
Corrections are automatically written to the DRAM
frame buffer.
1.7
Additional product support
•
Separate clock input to allow operation up to the
maximum 10 Mbytes/s
•
Fast synchronous SCSI-2 compatible
•
24-bit transfer counter for single transfers up to
16 Mbytes
•
High-speed 16-bit DMA interface to the buffer manager
DRAM
•
On-chip 48 mA SCSI drivers
•
Software compatible with members of the 53C90 family
•
Allows for SCAM support.
1.3
80C32 high-speed microcontroller
•
All control registers mapped into 80C32 special function
memory space
•
Dedicated S2B interface UART
•
Input clock synthesizer
•
Red book audio pass through.
2
GENERAL DESCRIPTION
•
33.87 MHz full system speed operation
•
Three timers/event counters
•
Programmable full duplex serial channel
•
Eight general purpose microcontroller I/O pins
•
External program ROM.
1.4
Front-end interface logic
The SAA7385 is a high integration ASIC that incorporates
all of the digital electronics necessary to connect a CD
decoder to a SCSI host. An 80C32 microcontroller and a
53CF94 SCSI controller are embedded in the ASIC.
The following functions are supported:
•
Input clock doubler
•
Block decoder
•
CRC checking of Mode 1 and Mode 2, Form 1 sectors
•
Red book audio pass through to SCSI
•
Buffer manager
•
Third-level error correction
•
Sub-code and Q-channel support
•
Dedicated S2B interface UART
•
Embedded 80C32 microcontroller
•
Embedded 53CF94 SCSI controller.
•
Full 8
×
speed hardware operation
•
Block decoder
•
Sector sequencer
•
CRC checking of Mode 1 and Mode 2, Form 1 sectors
•
212 ms watch-dog timer
•
Sub-code interface with synchronization
•
C-flag interface for absolute time stamp.
1996 Jun 19
3
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
The SAA7385 uses a 33.8688 MHz clock and is capable
of accepting data at eight times (n = 8 or 1.4 Mbytes/s) the
normal CD-ROM data rate.
Third level error correction hardware is included to
improve the correction efficiency of the system. The buffer
manager hardware utilizes a ten-level arbitration unit and
can stop the clock to the microcontroller to emulate a wait
condition when necessary.
The SAA7385 comprises five major functional blocks:
•
The 80C32 microcontroller is an industry standard core
•
The 53CF94 is an industry standard core
•
The front-end block connects to the external CD-60
based decoder and fully processes the incoming data
stream to provide bytes of data that are stored in the
external buffer
•
The buffer manager block provides the address
generation and timing control for the external DRAM
buffer
•
The ECC block performs the error correction functions in
hardware on the data in the DRAM buffer.
3
QUICK REFERENCE DATA
SYMBOL
V
DD
T
amb
T
stg
4
PARAMETER
digital supply voltage
operating ambient temperature
storage temperature
4.5
0
−55
MIN.
−
−
TYP.
5.0
SAA7385
Supply of this Compact Disc IC does not convey an
implied license under any patent right to use this IC in
any Compact Disc application.
MAX.
5.5
70
+150
V
UNIT
°C
°C
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SOT387-2
SAA7385GP
SQFP128 plastic quad flat package; 128 leads (lead length 1.6 mm);
body 14
×
20
×
2.8 mm
1996 Jun 19
4
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
5
BLOCK DIAGRAM
SAA7385
handbook, full pagewidth
256K
×
8 or 1M
×
8
DRAM BUFFER
BUFFER MANAGER
data
subcode
LAYERED
ERROR
CORRECTOR
BUFFER
MAPPER
53CF94
SCSI
SCSI
interface
DATA
CONVERTER
AND SUB-CODE
UART
data
CD
DECODER
subcode
C-flag
MICROCONTROLLER INTERFACE
SERVO
PROCESSOR
S2B serial interface
80C32 MICROCONTROLLER
DEBUG UART
debug
UART
SAA7385
MGE388
64K
×
8 ROM
Fig.1 Block diagram (simplified).
6 PINNING
All input, output and bidirectional signals are TTL level unless otherwise stated (Pull-Down = PD25 = 25
µA;
Pull-Up = PU25 = 25
µA,
PU400 = 400
µA;
Slew = S2 = 2 mA, S4 = 4 mA;
CMOS slew = CMOS S2 = CMOS 2 = 2 mA; SCSI pad = SCSI = 48 mA).
SYMBOL
DA2
DA3
DA4
V
SS1
DA5
DA6
DA7
DA8
DA9
V
DD1
1996 Jun 19
PIN
1
2
3
4
5
6
7
8
9
10
I/O
O
O
O
−
O
O
O
O
O
−
PAD
S4
S4
S4
−
S4
S4
S4
S4
S4
−
DESCRIPTION
DRAM address bus; bit DA2
DRAM address bus; bit DA3
DRAM address bus; bit DA4
ground 1
DRAM address bus; bit DA5
DRAM address bus; bit DA6
DRAM address bus; bit DA7
DRAM address bus; bit DA8
DRAM address bus; bit DA9
power supply 1
5
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