INTEGRATED CIRCUITS
DATA SHEET
SAA7390
High performance Compact
Disc-Recordable (CD-R) controller
Preliminary specification
File under Integrated Circuits, IC01
1996 Jul 02
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
CONTENTS
1
1.1
1.2
1.3
1.4
1.5
1.6
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
8
8.1
8.2
8.3
8.4
9
9.1
9.2
9.3
9.4
10
10.1
10.2
11
FEATURES
General
Interface logic (CD-ROM operation)
Hardware third-level error correction
Interface logic (CD-R operation)
DRAM buffer controller (256 kbytes
×
8,
1 Mbyte
×
8, 4 Mbytes
×
8)
Additional product support
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Input clock doubler
Block encoder
Front-end
Track descriptor block
Buffer manager
MICROCONTROLLER INTERFACE
Microprocessor interface status register
Microcontroller interface command register
Microprocessor interrupts
Microcontroller RAM organization
FRONT PANEL AND MISCELLANEOUS
CONTROL SIGNALS
S2B UART registers
SPI UART registers
Track Descriptor Block (TDB) generation
Miscellaneous control registers
FRONT-END
Minute-second frame addressing and header
information
Front-end status and control
BUFFER MANAGER
11.1
11.2
11.3
11.4
11.5
11.6
11.7
12
13
14
15
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
16
17
17.1
17.2
17.3
17.4
18
19
SAA7390
Front-end to buffer manager interface
Microcontroller to buffer manager interface
ECC to buffer manager interface
SCSI to buffer manager interface
Miscellaneous buffer manager considerations
Host interface related registers
CDB2 related registers
FRAME BUFFER ORGANIZATION
SUMMARY OF CONTROL REGISTER MAP
LIMITING VALUES
OPERATING CHARACTERISTICS
I
2
S-bus timing; data mode
EIAJ timing; audio mode
R-W timing (see Fig.17)
C-flag timing (see Fig.18)
S2B interface timing
SPI interface timing
Microprocessor interface
Host interface
DRAM interface (the SAA7390 is designed to
operate with standard 70 ns DRAMs)
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
1996 Jul 02
2
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
1
1.1
FEATURES
General
SAA7390
•
Dedicated Serial Peripheral Interface (SPI)
•
Third level error correction and encoding
•
80C32 microcontroller interface
•
53CF90 or 53CF92A/B fast SCSI processor interface
(may also use ATAPI processor).
2
GENERAL DESCRIPTION
•
8× speed CD-ROM, 4× speed Compact
Disc-Recordable (CD-R) controller
•
16.9 Mbytes/s burst rate to host controller
•
High performance CD-ROM and CD-R interface logic
•
128 pin QFP package.
1.2
Interface logic (CD-ROM operation)
•
Full 8× speed hardware operation
•
Block decoder
•
Sector sequencer
•
CRC checking of Mode 1 and Mode 2, Form 1 sectors
•
212 ms watch-dog timer
•
Sub-code interface with synchronization
•
C-flag interface for absolute time stamp.
1.3
Hardware third-level error correction
The SAA7390 is a high integration ASIC that incorporates
all of the logic necessary to connect a CD-60 based
decoder to a SCSI or ATAPI host. It also supports a data
path from the host to the CDCEP (compact disc encoder)
for CD-R applications. An 80C32 microcontroller and a
53CF94/92A (or an ATAPI interface device) are required
to provide the full block encode/decode functions. The
following functions are supported:
•
Input clock doubler
•
Block encoder (using a modified CDB2)
•
Block decoder
•
CRC checking of Mode 1 and Mode 2, Form 1 sectors
•
Red book audio pass through to SCSI or ATAPI
•
Sub-code and Q-channel support
•
Dedicated S2B interface UART
•
Dedicated SPI interface UART
•
Up to 4 Mbytes DRAM buffer manager
•
Third-level error correction and encoding
•
Automatic storage of audio and data
•
80C32 microcontroller interface
•
53CF90 or 53CF92A/B fast SCSI or Wapiti ATAPI
processor interface.
The SAA7390 uses a 33.8688 MHz clock and is capable
of accepting data at eight times (n = 8 or 1.4 Mbytes/s) the
normal CD-ROM data rate. The minimum host burst rate
capability of the SAA7390 is 5 Mbytes/s.
Third level error correction hardware is included to
improve the correction efficiency of the system. The buffer
manager hardware utilizes a ten-level arbitration unit and
can stop the clock to the static microcontroller to emulate
a wait condition when necessary. The host interface is
capable of burst rates to 16.9 Mbytes/s.
•
Third-level correction provides superior performance in
unfavourable conditions
•
Full hardware error correction to reduce microcontroller
overhead
•
Corrections are automatically written to the DRAM
frame buffer.
1.4
Interface logic (CD-R operation)
•
Block encoder (using a modified CDB2).
1.5
DRAM buffer controller (256 kbytes
×
8,
1 Mbyte
×
8, 4 Mbytes
×
8)
•
DRAM buffer manager
•
Ten level arbitration logic
•
Utilizes low cost 70 ns DRAMs
•
Page mode DRAM access for high-speed error
correction and host interface data transfers
•
Data organization by 3 kbytes frames.
1.6
Additional product support
•
Input clock doubler
•
All control registers mapped into 80C32 special function
memory space
•
Red book audio pass through to host interface
•
Sub-code and Q-channel support
1996 Jul 02
3
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
The SAA7390 comprises four major functional blocks:
•
The front-end block connects to the external CD-60
based decoder and fully processes the incoming data
stream
•
The buffer manager block provides the address
generation and timing control for the external DRAMs
•
The ECC block performs the error correction functions in
hardware on the data stored in the DRAM buffer.
•
The block encoder function (realized via a modified
CDB2) serializes the data from the buffer, appends the
sync pattern, header, sub-header, third level ECC parity
and EDC bytes as necessary, performs the required
scrambling and outputs them to the CDCEP using a
special data clock (98 clock cycles per word selection
period).
3
QUICK REFERENCE DATA
SYMBOL
V
DD
T
amb
T
stg
4
PARAMETER
digital supply voltage
operating ambient temperature
storage temperature
4.5
0
−55
MIN.
−
−
TYP.
5.0
SAA7390
MAX.
5.5
70
+150
V
UNIT
°C
°C
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SOT387-2
SAA7390GP
(1)
Note
SQFP128 plastic quad flat package; 128 leads (lead length 1.6 mm);
body 14
×
20
×
2.8 mm
1. This device uses a Symbios logic package.
1996 Jul 02
4
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
5
BLOCK DIAGRAM
SAA7390
handbook, full pagewidth
256K
×
8 to 4M
×
8
DRAM BUFFER
BUFFER MANAGER
data
subcode
LAYERED
ERROR
CORRECTOR
BUFFER
MAPPER
GENERIC
EXTERNAL
INTERFACE
SCSI
or
ATAPI
interface
DATA
CONVERTER
AND SUB-CODE
UART
data
subcode
C-flag
ENCODE
CD
DECODER
MICROCONTROLLER INTERFACE
BASIC
ENGINE
WRITE I/F
SAA7390
SPI UART
S2B UART
S2B
interface
MGE518
SPI
interface
80C32 MICROCONTROLLER
128K
×
8 ROM
Fig.1 Block diagram (simplified).
6 PINNING
All input and bidirectional signals are TTL level with Schmitt-trigger logic, with the exception of OSCIN. All output
signals are TTL levels unless otherwise stated. (PD = internal pull-down; PU = internal pull-up).
SYMBOL
DA0
DA1
DA2
V
SS1
DA3
DA4
DA5
V
SS2
DA6
PIN
1
2
3
4
5
6
7
8
9
I/O
O
O
O
−
O
O
O
−
O
TYPE
DESCRIPTION
DRAM address bus; bit DA0
DRAM address bus; bit DA1
DRAM address bus; bit DA2
ground 1
DRAM address bus; bit DA3
DRAM address bus; bit DA4
DRAM address bus; bit DA5
ground 2
DRAM address bus; bit DA6
1996 Jul 02
5
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