INTEGRATED CIRCUITS
DATA SHEET
SAA7391
ATAPI CD-R block
encoder/decoder
Objective specification
File under Integrated Circuits, IC01
1997 Aug 01
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
CONTENTS
1
2
2.1
2.2
2.3
2.4
2.5
2.6
3
4
5
6
6.1
7
7.1
7.1.1
7.2
7.2.1
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.4.1
7.4.2
7.4.3
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
FEATURES
GENERAL DESCRIPTION
Memory mapped control registers
Error correction features
Host interface features
Buffer memory organisation
Subcode handling features
Multimedia output audio control features
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
Detailed description of pin functions
FUNCTIONAL DESCRIPTION
Memory field description
DVD-ROM memory field information
CD input control registers
Registers associated with data in process
Multimedia output interface
Subcode input block
Subcode mode transmit control register
General description of the multimedia output
interface
IEC 958/EBU output
Memory-to-memory block copy function
Interrupt registers
Interrupt 1
Interrupt 2
UART interrupt
Host interface
Introduction
Description of the host interface block
Description of the host interface registers
Transfer counter
Packet size store
Sequencer status
Host interface DMA special bits
Automatic block pointer reload programming
DMA transfer programming of the host
interface
Generic interface operation
7.6
7.6.1
7.6.2
7.7
7.7.1
7.7.2
7.7.3
7.8
7.8.1
7.9
7.9.1
7.10
7.10.1
7.10.2
7.10.3
8
9
10
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.3
11.4
12
13
14
15
15.1
15.2
15.3
15.4
16
17
7.5.11
7.5.12
7.5.13
SAA7391
DMA transfers in generic mode
Normal DMA mode
Burst DMA mode using multiplexed bus
configuration
Microcontroller interface
Kernel based firmware
16-bit registers automatic read and write
8051 CPU and memory management functions
Sub-CPU bus access timing
Buffer memory organisation
Subpage
External memory interface
DRAM interface configuration register
UART for communication with CD engine
UART basic engine interface
Clock generation control
Crystal oscillator
Sub-CPU clock control register
SAA7391 system clock control registers
LIMITING VALUES
THERMAL CHARACTERISTICS
CHARACTERISTICS
TIMING CHARACTERISTICS
External memory interface timing
Host interface timing
Host interface ATAPI PIO and DMA timing
ATA bus timing
Ultra DMA operation and timing
Ultra DMA read/write timing
Sub-CPU interface timing
UART timing
APPENDIX A
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
1997 Aug 01
2
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
1
FEATURES
SAA7391
The reading and writing of 16-bit registers within the device
can be performed by two separate 8-bit reads, where the
second byte data is latched at the same time as the first
byte is read.
2.2
Error correction features
•
Supports real time error detection and correction in
hardware. Error correction to n = 27, error detect to
n = 30 and raw data transfer to n = 32.
•
CD-R to CD-n greater than 8. Internal operation is
faster, but firmware and physical (laser/media) factors
limit the speed
•
DVD-ROM supported in combination with the SAA7335
•
Direct generic interface to external Small Computer
Systems Interface (SCSI) controller devices
•
Operates with up to 16 Mbytes DRAM
– Hyper-page DRAM up to 33 Mbytes words/s burst
– Fast-page DRAM at up to 17.5 Mbytes words/s burst
•
Has fixed n = 1 or n = 2 rate (44.1 or 88.2 kHz) I
2
S-bus
multimedia output for simple audio/video output;
features for CAV/quasi-CLV support
– Supports Philips multimedia audio CODEC
– Provides ‘SHOARMA’ Red Book audio buffer
•
IEC 958 (SPDIF, AES/EBU and DOBM) output with
Q-W subcode and programmable category code, output
at n = 1 rate
•
Device registers are memory mapped for faster direct
access to the chip
•
Provides direct access from sub-CPU to buffer RAM to
support scratchpad accesses. This eliminates the need
for extra RAM chips in the system
•
Automatic sequencing of ATAPI packet command
protocol, including command termination
•
Automated data transfers to and from the host using
PIO, DMA and ultra DMA.
2
GENERAL DESCRIPTION
The SAA7391 has an on-chip 36 kbits memory that is used
as a buffer memory for error and erasure correction
processing. This buffer memory reduces the number of
external RAM accesses that are needed for error
correction and thus allows for an increased rate of data
throughput.
The error corrector is switchable between two-pass,
single-pass [both with Error Detection/Correction (EDC)]
and EDC only modes to further improve throughput.
The presence of the full error corrector removes the need
for firmware based control of the error corrector’s
operation.
2.3
Host interface features
The SAA7391 has an ATAPI host interface that may be
directly connected to the ATAPI bus thereby reducing the
need for external support devices. It supports PIO Mode 4
transfer and Mode 0 ultra DMA. This interface can also be
configured as a generic DMA interface for use with
external host interface devices (e.g. SCSI controller).
The DMA interface has the following features:
•
ATAPI command packets are automatically loaded into
the command FIFO
•
Data transfer to the host is automatically sequenced to
reduce inter-block latencies and improve host CPU
utilisation
•
Host data transfer rate is independent of error corrector
operation and the data input path
•
The host interface features automatic determination of
block length for Mode 2, Form 1 and Form 2 sectors.
The block length transferred is programmable.
•
The host interface can transfer up to 3 sub-blocks per
sector, with each sub-block being transferred dependent
on the Form bit. Automatic reload of sub-block pointers
and unconditional transfer are supported.
The SAA7391 is a block decoder/encoder and buffer
manager for high-speed CD-ROM/CD-R functions, that
integrates real time error correction and detection and
bidirectional ATAPI transfer functions into a single chip.
2.1
Memory mapped control registers
The SAA7391 device has a large number of memory
mapped registers. These are arranged so that high-level
languages see the registers as external byte or 16-bit
integer quantities. The block addressing of the SAA7391
facilitates the use of pairs of 16-bit quantities to represent
addresses.
1997 Aug 01
3
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
2.4
Buffer memory organisation
SAA7391
•
Subcodes are written into memory together with their
associated sector data.This eases the provision of
specialist features, for example CD + G or Karaoke CD
applications.
•
All channels of subcode are de-interleaved
•
The Q channel is also Cyclic Redundancy Checked
(CRC) for increased reliability
•
When operating in 3-wire subcode mode, it is possible
to control or read the P bit in the P-W subcode stream.
2.6
Multimedia output audio control features
Memory is mapped as a 16-bit block number and 12-bit
offset into that block. The block oriented memory structure
permits the use of 16-bit pointers in software thereby
minimising the overhead of accessing memory.
The address can be found from the following equation:
address = block number
×
2560 + offset.
The microcontroller sees the SAA7391 as a memory
mapped peripheral, with control and status registers
appearing in the upper address space.
The lowest 52 kbytes (48 kbytes + 4 kbytes) of the
8051 microcontroller external address space is mapped as
a window into the memory on a user-specified 1 kbyte
boundary within the buffer RAM. This can be used as a
scratchpad memory.
The next 4 kbytes is separately mapped as a window into
the memory on a user-specified 1 kbyte boundary within
the RAM.
The next 7.5 kbytes of the external data space consists of
three independently addressed memory segments for
accessing block data, subcode information and block
headers.
The registers of the SAA7391 are mapped into the top
256 bytes of external data space.
2.5
Subcode handling features
The I
2
S-bus input may be processed before feeding to the
multimedia audio output in several simple ways:
•
As audio is transferred via the buffer memory, it is not
necessary to have the CD-DSP I
2
S-bus input at exactly
the audio n = 1 or video n = 2 rate. Any faster speed will
work because the buffer RAM is used as a FIFO.
•
Both channels may be independently controlled. The left
channel output may be sourced from zero (digital
silence), left or right input; this also applies for the right
channel output. This permits basic audio switching and
channel swapping.
•
IEC 958 (SPDIF, AES/EBU and DOBM) output with
Q-W subcode and programmable category code, can be
output from the same CD-DSP I
2
S-bus data source.
The writing of data into the buffer RAM is aligned to the
absolute time sync marker with the following features:
3
QUICK REFERENCE DATA
SYMBOL
V
DDD(core)
V
DDD(pad)
I
DDD
f
xtal
T
amb
T
stg
4
PARAMETER
digital core supply voltage
digital peripheral supply voltage
supply current
crystal frequency
operating ambient temperature
storage temperature
3.0
V
DDD(core)
tbf
8
0
−55
MIN.
3.3
5.0 or 3.3
60
8.4672, 16.9344
or 33.8688
−
−
TYP.
MAX.
3.6
5.0
tbf
35
70
+125
UNIT
V
V
mA
MHz
°C
°C
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
LQFP144
DESCRIPTION
plastic low profile quad flat package; 144 leads;
body 20
×
20
×
1.4 mm
4
VERSION
SOT486-1
SAA7391H
1997 Aug 01
Philips Semiconductors
Objective specification
ATAPI CD-R block encoder/decoder
5
BLOCK DIAGRAM
SAA7391
handbook, full pagewidth
EXTERNAL
DRAM
I
2
S-bus to CD-R
I
2
S-bus
from CD-DSP
DRIVE
INTERFACE
ENCODER
ERROR
CORRECTOR
MEMORY
PROCESSOR
ATAPI
HOST
INTERFACE
IDE-bus
subcode to CD-R
subcode
from CD-DSP
I
2
S-bus to DAC
IEC 958
SUBCODE
INTERFACE
SAA7391
MULTIMEDIA
INTERFACE
SYSTEM
CLOCK
GENERATOR
TEST
CONTROL
BLOCK
SUB-CPU
INTERFACE
MGK506
master clock
clock
sub-CPU
Fig.1 The SAA7391 internal block diagram.
1997 Aug 01
5
Microchip MCU
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