Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
CONTENTS
1
1.1
1.2
2
3
4
5
6
7
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
FEATURES
Hardware
Software
APPLICATIONS
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
Signal path for level information
Level ADC switch mode integrator (pin CINT)
Internal ground reference for the level ADC
(pin V
DACNL
)
Common mode reference voltage for RDS
ADC, ADC level and buffers (pin V
refRDS
)
Signal path for audio/MPX and stereo decoder
Mono/stereo switching
The automatic lock system
Input sensitivity for FM
Common mode reference voltage for MPX
ADC and buffers (pin V
refMPX
)
Supply voltages for the switch capacitor DACs
of the FMMPX ADC and FMRDS ADC
(pins V
DACNM
and V
DACPM
)
Noise level
TAPE/AUX de-multiplex
Signal-to-noise considerations
Channel separation correction
Input selection switches
Analog inputs supply
Digitally controlled sampling clock (DCS)
Survey of the DCS clock settings in different
modes
Synchronization with the core
Interference absorption circuit
IAC testing
ANALOG OUTPUTS
Digital-to-Analog Converters
Upsample filter
Volume control
Power-on mute
Power-off plop suppression
Internal reference buffer amplifier of the DAC
(pin V
ref
)
Internal DAC current reference
Analog outputs supply
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
11
12
13
14
15
15.1
15.2
15.3
15.4
15.5
15.6
16
17
18
19
19.1
19.2
19.3
19.4
20
21
22
9.9
9.10
9.11
10
10.1
10.2
10.3
10.4
Clock circuit and oscillator
Crystal oscillator supply
External control pins
I
2
S-BUS DESCRIPTION
SAA7707H
I
2
C-bus control (SCL and SDA pins)
I
2
S-bus description
Communication with external digital audio
sources (DCC + CD-WS/CL/Data pins)
Communication with external processors and
other devices (EXWS/CL/EXDAT1 and
EXDAT2)
Relationship between external input and
external output
RDS decoder (RDSCLK and RDSDAT)
Clock and data recovery
Timing of clock and data signals
Buffering of RDS data
Buffer interface
DSP reset
Power supply connection and EMC
LIMITING VALUES
THERMAL CHARACTERISTICS
DC CHARACTERISTICS
AC CHARACTERISTICS
I
2
C-BUS CONTROL AND COMMANDS
Characteristics of the I
2
C-bus
Bit transfer
START and STOP conditions
Data transfer
Acknowledge
I
2
C-bus format
SOFTWARE DESCRIPTION
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
1997 May 30
2
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
1
1.1
FEATURES
Hardware
2
APPLICATIONS
SAA7707H
•
Car radio
•
Car audio systems.
3
GENERAL DESCRIPTION
•
Bitstream 3rd-order Sigma-Delta Analog-to-Digital
Converters (ADCs) with anti-aliasing broadband input
filters
•
Digital-to-Analog Converters (DACs)with four times
oversampling and noise shaping
•
Digital stereo decoder
•
Improved digital Interference Absorption Circuit (IAC)
•
RDS processing with optional 16-bit buffer via separate
channel (two-tuner radio possible)
•
Auxiliary analog CD input (CD-walkman, speech,
economic CD-changer, etc.)
•
Two separate full
performance interfaces
I
2
S-bus
CD and DCC high
The SAA7707H performs all the signal functions in front of
the power amplifiers and behind the AM and FMMPX
demodulation of a car radio or the tape input.
These functions are:
•
Interference absorption
•
Stereo decoding
•
RDS decoding
•
FM and AM weak signal processing (soft mute, sliding
stereo, etc.)
•
Dolby-B tape noise reduction
•
The audio controls (volume, balance, fader, tone and
dynamics compression).
Some functions have been implemented in hardware
(stereo decoder, RDS decoder and IAC) and are not freely
programmable. Digital audio signals from external sources
with I
2
S-bus formats are accepted. There are four
independent analog output channels. This enables, in
special system configurations, separate tone and
equalization control for front and rear speakers.
The CDSP contains a basic program that enables a set
with:
•
AM/FM reception
•
Sophisticated FM weak signal functions
•
Music Search detection for Tape (MSS)
•
Dolby-B tape noise reduction system
•
CD play with compressor function
•
Separate bass and treble tone control and fader/balance
control.
For high-end sets with special and more sophisticated
features, an additional Digital Signal Processor (DSP) can
be connected. Examples of such features are:
•
Noise-dependent volume control
•
10-band graphic equalizer
•
Audio spectrum analyzer on display
•
Signal delay for concert hall effects.
•
Expandable with additional Digital Signal Processors
(DSPs) for sophisticated features through an I
2
S-bus
gateway
•
Audio output short-circuit protected
•
I
2
C-bus controlled
•
Analog tape input
•
Operating ambient temperature from
−40
to +85
°C.
1.2
Software
•
Improved FM weak signal processing
•
Integrated 19 kHz MPX filter and de-emphasis
•
Electronic adjustments: FM/AM level, FM channel
separation and Dolby level
•
Baseband audio processing (treble, bass, balance,
fader and volume)
•
Dynamic loudness or bass boost
•
Stereo one-band parametric equalizer
•
Audio level meter for an automatic leveller
(in combination with microcontroller)
•
Tape equalization (DCC analog playback)
•
Music Search detection for Tape (MSS)
•
Pause detection for RDS updates
•
Dolby-B tape noise reduction
•
Adjustable dynamics compressor
•
CD and DCC de-emphasis processing
•
Signal level, noise and multi-path detection for RDS
(I
2
C-bus command)
•
Improved AM reception.
1997 May 30
3
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
4
QUICK REFERENCE DATA
SYMBOL
V
DDD(tot)
I
DDD(tot)
P
tot
S/N
PARAMETER
total DC supply voltage
total DC supply current
total power dissipation
level ADC signal-to-noise
ratio
CONDITIONS
all supply pins
maximum activity of the
DSP; f
xtal
= 36 MHz
maximum activity of the
DSP; f
xtal
= 36 MHz
RMS value;
unweighted;
B = 0 to 29 kHz;
maximum input
not multiplexed;
B = 19 kHz;
V
i
= 1 V (RMS)
multiplexed;
unweighted;
B = 19 kHz; 1 V (RMS)
ADC signal-to-noise ratio for
FM-RDS
V
iFS
THD
V
imc(rms)
ADC full-scale input voltage
total harmonic distortion
pins 62 and 71 to 75
maximum conversion input
voltage level pins 62 and
71 to 75 (RMS value)
DAC resolution
−
−
48
MIN.
4.75
5
160
0.8
54
TYP.
SAA7707H
MAX.
5.5
200
1.1
−
UNIT
V
mA
W
dB
ADC signal-to-noise ratio
81
85
−
dB
72
76
−
dB
RMS value; B = 6 kHz; 56
unweighted; f
c
= 57 kHz
V
DDA1
= 4.75 to 5.5 V
f
i
= 1 kHz;
V
i
= 1 V (RMS)
THD < 1%
1.05V
DDA1
−
−
1.1
−
1.1V
DDA1
−71
0.03
−
−
1.15V
DDA1
−61
0.09
−
dB
V
dB
%
V
RES
(THD + N)/S
−
18
−70
−
−60
bits
dB
total harmonic distortion plus R
L
> 5 kΩ AC;
−
noise-to-signal ratio for DAC R
fb
= 2.7 kΩ; f
i
= 1 kHz;
and operational amplifiers
R
ref
= 18 kΩ;
V
oFS
= 2.8 V (p-p);
maximum I
2
S-bus signal
dynamic range of DAC
digital silence of DAC
crystal frequency DSP part
f
i
= 1 kHz;
−60
dB;
A-weighted
f
i
= 20 Hz to 17 kHz;
A-weighted
92
−
−
DR
DS
f
xtalDSP
5
102
−110
36.86
−
−100
−
dB
dB
MHz
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
QFP80
DESCRIPTION
plastic quad flat package; 80 leads (lead length 1.95 mm);
body 14
×
29
×
2.8 mm
VERSION
SOT318-2
SAA7707H
1997 May 30
4
微控制器 MCU
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