C16x-Family of
High-Performance CMOS 16-Bit Microcontrollers
Preliminary
SAB 80C166W/83C166W / 83C166W
SAB 80C166W/
83C166W/
83C166W
16-Bit Microcontroller
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High Performance 16-bit CPU with 4-Stage Pipeline
100 ns Instruction Cycle Time at 20 MHz CPU Clock
500 ns Multiplication (16
×
16 bits), 1
µs
Division (32 / 16 bit)
Enhanced Boolean Bit Manipulation Facilities
Register-Based Design with Multiple Variable Register Banks
Single-Cycle Context Switching Support
Up to 256 KBytes Linear Address Space for Code and Data
1 KByte On-Chip RAM
32 KBytes On-Chip ROM (SAB 83C166W only)
Programmable External Bus Characteristics for Different Address Ranges
8-Bit or 16-Bit External Data Bus
Multiplexed or Demultiplexed External Address/Data Buses
Hold and Hold-Acknowledge Bus Arbitration Support
512 Bytes On-Chip Special Function Register Area
Idle and Power Down Modes
8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event
Controller (PEC)
16-Priority-Level Interrupt System
10-Channel 10-bit A/D Converter with 9.7
µs
Conversion Time
16-Channel Capture/Compare Unit
Two Multi-Functional General Purpose Timer Units with 5 Timers
Two Serial Channels (USARTs)
Programmable Watchdog Timer
Up to 76 General Purpose I/O Lines
Direct clock input without prescaler
Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,
Programming Boards
On-Chip Bootstrap Loader
100-Pin Plastic MQFP Package (EIAJ)
Semiconductor Group
1
10.94
SAB 80C166W/83C166W
Introduction
The SAB 80C166W/83C166W is a representative of the Siemens SAB 80C166 family of full
featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million
instructions per second) with high peripheral functionality and enhanced IO-capabilities. These
devices derive the CPU clock signal (operating clock) directly from the on-chip oscillator without
using a prescaler. This reduces the device’s EME.
SAB
80C166W
Figure 1
Logic Symbol
Ordering Information
Type
SAB 83C166W-5M
SAB 83C166W-5M-
T3
SAB 83C166W-5M-
T4
SAB 80C166W/
83C166W-M
Ordering Code Package
On Request
Q67120-D...
Q67120-D...
On Request
Function
P-MQFP-100-2 16-bit microcontroller, 0 ˚C to +70 ˚C,
1 KByte RAM and 32 KByte ROM
P-MQFP-100-2 16-bit microcontroller, -40 ˚C to +85 ˚C,
1 KByte RAM and 32 KByte ROM
P-MQFP-100-2 16-bit microcontroller, -40 ˚C to +110 ˚C
1 KByte RAM and 32 KByte ROM
P-MQFP-100-2 16-bit microcontroller, 0 ˚C to +70 ˚C
1 KByte RAM
Semiconductor Group
2
SAB 80C166W/83C166W
Type
SAB 80C166W/
83C166W-M-T3
SAB 80C166W/
83C166W-M-T4
Ordering Code Package
Q67120-C864
Q67120-C917
Function
P-MQFP-100-2 16-bit microcontroller, -40 ˚C to +85 ˚C
1 KByte RAM
P-MQFP-100-2 16-bit microcontroller, -40 ˚C to +110 ˚C
1 KByte RAM
Note:
The ordering codes (Q67120-D...) for the Mask-ROM versions are defined for each product
after verification of the respective ROM code.
Pin Configuration Rectangular P-MQFP-100-2
(top view)
SAB 80C166W/
Figure 2
Semiconductor Group
3
SAB 80C166W/83C166W
Pin Definitions and Functions
Pin
No.
16 - 17
Symbol
P4.0 –
P4.1
Input (I)
Function
Output (O)
I/O
Port 4
is a 2-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
P4.0
A16
Least Significant Segment Addr. Line
P4.1
A17
Most Significant Segment Addr. Line
XTAL1:
Input to the oscillator amplifier and input to the
internal clock generator
XTAL2:
Output of the oscillator amplifier circuit.
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC Characteristics
must be observed.
External Bus Configuration
selection inputs. These pins are
sampled during reset and select either the single chip mode or
one of the four external bus configurations:
BUSACT EBC1 EBC0 Mode/Bus Configuration
0
0
0
8-bit demultiplexed bus
0
0
1
8-bit multiplexed bus
0
1
0
16-bit muliplexed bus
0
1
1
16-bit demultiplexed bus
1
0
0
Single chip mode
1
0
1
Reserved.
1
1
0
Reserved.
1
1
1
Reserved.
ROMless versions must have pin BUSACT tied to ‘0’.
Reset Input
with Schmitt-Trigger characteristics. A low level
at this pin for a specified duration while the oscillator is running
resets the SAB 80C166W/83C166W. An internal pullup
resistor permits power-on reset using only a capacitor
connected to
V
SS
.
Internal Reset Indication Output.
This pin is set to a low
level when the part is executing either a hardware-, a
software- or a watchdog timer reset. RSTOUT remains low
until the EINIT (end of initialization) instruction is executed.
16
17
20
19
XTAL1
XTAL2
O
O
I
O
22
23
24
BUSACT, I
EBC1,
I
EBC0
I
27
RSTIN
I
28
RSTOUT
O
Semiconductor Group
4
SAB 80C166W/83C166W
Pin Definitions and Functions
(cont’d)
Pin
No.
29
Symbol
NMI
Input (I)
Function
Output (O)
I
Non-Maskable Interrupt
Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI pin
must be low in order to force the SAB 80C166W/83C166W to
go into power down mode. If NMI is high, when PWRDN is
executed, the part will continue to run in normal mode.
If not used, pull NMI high externally.
Address Latch Enable
Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
External Memory Read Strobe.
RD is activated for every
external instruction or data read access.
Port 1 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 1 is used as the 16-bit address bus (A)
in demultiplexed bus modes and also after switching from a
demultiplexed bus mode to a multiplexed bus mode..
Port 5
is a 10-bit input-only port with Schmitt-Trigger
characteristics. The pins of Port 5 also serve as the (up to 10)
analog input channels for the A/D converter, where P5.x
equals ANx (Analog input channel x).
Port 2
is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
The following Port 2 pins also serve for alternate functions:
P2.0
CC0IO
CAPCOM: CC0 Cap.-In/Comp.Out
...
...
...
P2.13
CC13IO CAPCOM: CC13 Cap.-In/Comp.Out,
BREQ
External Bus Request Output
P2.14
CC14IO CAPCOM: CC14 Cap.-In/Comp.Out,
HLDA
External Bus Hold Acknowl. Output
P2.15
CC15IO CAPCOM: CC15 Cap.-In/Comp.Out,
HOLD
External Bus Hold Request Input
29
ALE
O
26
30 - 37
40 - 47
RD
P1.0 –
P1.15
O
I/O
48 - 53
56 - 59
P5.0 –
P5.9
I
I
62 - 77
P2.0 –
P2.15
I/O
62
75
76
77
I/O
I/O
O
I/O
O
I/O
I
Semiconductor Group
5
FPGA/CPLD
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