ICs for Communications
Enhanced Serial Communication Controller with 8 Channels
ESCC8
SAB 82538
SAF 82538
Version 2.2
User’s Manual 03.95
Edition 03.95
This edition was realized using the software
system FrameMaker
‚
.
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
©
Siemens AG 1995.
All Rights Reserved.
Attention please!
As far as patents or other rights of third par-
ties are concerned, liability is only assumed
for components, not for applications, pro-
cesses and circuits implemented within com-
ponents or assemblies.
The information describes the type of compo-
nent and shall not be considered as assured
characteristics.
Terms of delivery and rights to change design
reserved.
For questions on technology, delivery and
prices please contact the Semiconductor
Group Offices in Germany or the Siemens
Companies and Representatives worldwide
(see address list).
Due to technical requirements components
may contain dangerous substances. For in-
formation on the types in question please
contact your nearest Siemens Office, Semi-
conductor Group.
Siemens AG is an approved CECC manufac-
turer.
Packing
Please use the recycling operators known to
you. We can also help you – get in touch with
your nearest sales office. By agreement we
will take packing material back, if it is sorted.
You must bear the costs of transport.
For packing material that is returned to us un-
sorted or which we are not obliged to accept,
we shall have to invoice you for any costs in-
curred.
Components used in life-support devices
or systems must be expressly authorized
for such purpose!
Critical components
1
of the Semiconductor
Group of Siemens AG, may only be used in
life-support devices or systems
2
with the ex-
press written approval of the Semiconductor
Group of Siemens AG.
1 A critical component is a component used
in a life-support device or system whose
failure can reasonably be expected to
cause the failure of that life-support device
or system, or to affect its safety or effec-
tiveness of that device or system.
2 Life support devices or systems are in-
tended (a) to be implanted in the human
body, or (b) to support and/or maintain
and sustain human life. If they fail, it is rea-
sonable to assume that the health of the
user may be endangered.
SAB 82538
SAF 82538
Revision History:
Previous Version:
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Version
01.94)
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Current Version: 03.95
User’s Manual 01.94
Subjects (changes since last revision)
V
DD
and
V
SS
pin configuration
RD/DS Description
RES pin number
DACKx Description
V
DD
and
V
SS
numbers
Transparent Mode 1, Address Recognition
Transmitter Interrupts, Figure 21
Transmitter Interrupts, Figures 23/24
Transmitter Interrupts, Figures 28/29
Note in description of Clock Mode 5
CD-signal, Figure 35
Interrupt Driven Reception Sequence, Figure 47
CCR4 Register Addresses
RHCR Register Description
XBC Register Description
XMR Interrupt Description
RFRD Command Description
RBC Register Description
TCD Interrupt Description
RFRD Command Description
RBC Register Description
TCD Interrupt Description
Timings
t
p (DRT)
,
t
SU (IE)
Timing
t
SU (IE)
Timing
t
p (PV-INT)
Number of Timing
t
C (XC)
Minor Misprints
Data Classification
Maximum Ratings
Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible
damage to the integrated circuit.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specify mean values expected over the production spread. If not otherwise
specified, typical characteristics apply at
T
A
= 25 ˚C and the given supply voltage.
Operating Range
In the operating range the functions given in the circuit description are fulfilled.
For detailed technical information about
"Processing Guidelines"
and
"Quality Assurance"
for ICs, see our
"Product Overview".
General Information
Table of Contents
Page
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.2.1
1.4.2.2
1.4.2.3
1.4.2.4
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.3.1
2.2.3.2
2.2.3.3
2.2.4
2.2.5
2.3
2.3.1
2.3.2
2.3.2.1
2.3.2.2
2.3.2.3
2.3.3
2.3.4
2.3.4.1
2.3.4.2
2.3.4.3
2.3.4.4
2.3.4.5
2.3.4.6
2.3.4.7
2.3.4.8
2.3.4.9
General Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Pin Definitions and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
General Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
ESCC8 with SAB 80188 Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
ESCC8 with 80386 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
ESCC8 with MC 68020, 68030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Interrupt Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Data Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Interrupt Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Vectored Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
FIFO Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
HDLC/SDLC Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Procedural Support (Layer-2 Functions) . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Full-Duplex LAPB/LAPD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Half-Duplex SDLC-NRM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
SDLC Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Shared Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Preamble Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
CRC-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Extended Transparent Transmission and Reception . . . . . . . . . . . . . . . . . . .69
Cyclic Transmission (Fully Transparent) . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Continuous Transmission (DMA Mode only) . . . . . . . . . . . . . . . . . . . . . . . . .70
Receive Length Check Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
One Bit Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
CRC ON/OFF Feature (version 2 upward) . . . . . . . . . . . . . . . . . . . . . . . . . .71
Semiconductor Group
4
General Information
Table of Contents
(cont’d)
Page
2.3.4.10 Receive Address Handling (version 2 upward) . . . . . . . . . . . . . . . . . . . . . . .72
2.4
Asynchronous Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
2.4.1
Character Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
2.4.2
Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
2.4.2.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
2.4.2.2 Storage of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
2.4.3
Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
2.4.4
Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
2.4.4.1 Break Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
2.4.4.2 Flow Control by XON/XOFF (version 2 upward) . . . . . . . . . . . . . . . . . . . . . .75
2.4.4.3 Continuous Transmission (DMA Mode only) . . . . . . . . . . . . . . . . . . . . . . . . .77
2.5
Character Oriented Serial Mode (MONOSYNC/BISYNC) . . . . . . . . . . . . . . .78
2.5.1
Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
2.5.2
Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
2.5.3
Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
2.5.4
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
2.5.4.1 Preamble Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
2.5.4.2 Continuous Transmission (DMA Mode only) . . . . . . . . . . . . . . . . . . . . . . . . .81
2.5.4.3 CRC Parity Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
2.6
Serial Interface (Layer-1 functions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.6.1
Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
2.6.2
Clock Recovery (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
2.6.3
Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
2.6.3.1 Bus Access Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
2.6.3.2 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
2.6.3.3 Priority (HDLC/SDLC Mode Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
2.6.3.4 Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
2.6.3.5 Functions of RTS Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
2.6.4
Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
2.6.5
Modem Control Functions (RTS/CTS, CD) . . . . . . . . . . . . . . . . . . . . . . . . . .97
2.6.5.1 RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
2.6.5.2 Carrier Detect (CD) Receiver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
2.6.6
Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
2.7
Universal Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
3
3.1
3.2
3.3
3.3.1
3.3.1.1
3.3.1.2
Operational Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Operational Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
5
Semiconductor Group