电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

PT7M6315US46D3

产品描述Supervisory Circuit
文件大小383KB,共6页
制造商Pericom Semiconductor Corporation (Diodes Incorporated)
官网地址https://www.diodes.com/
下载文档 全文预览

PT7M6315US46D3概述

Supervisory Circuit

文档预览

下载PDF文档
PT7M6315US
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Supervisory Circuit
Features
Highly accurate:
1.5%
(25°
C)
Detect voltage range: 1.8 to 5V in 100mV
increments
Operating voltage range: 1.0V ~ 5.5V
Operating temperature range: -40° to + 85°
C
C
Detect voltage temperature characteristics:
2.5% 
TYP
Output configuration: N-channel open drain
Three reset timeout period available:
typical 1.6ms for PT7M6315USxxD1;
typical 26ms for PT7M6315USxxD2;
typical 200ms for PT7M6315USxxD3;
typical 1570ms for PT7M6315USxxD4;
Description
The series are designed to monitor power supplies in µ
P
and digital systems. It provides excellent circuit
reliability and low cost by eliminating external
components and adjustments, and a debounced manual
reset input.
This device performs a single function: it asserts a reset
signal whenever the V
CC
supply voltage falls below a
preset threshold or whenever manual reset is asserted.
Reset remains asserted for an internally programmed
interval (reset timeout period) after V
CC
has risen above
the reset threshold or manual reset is deasserted.
The PT7M6315USxx are open-drain RESET output.
They can be pulled up to a voltage higher than V
CC
.
The serials come with factory-trimmed reset threshold
voltages in 100mV increments from 1.8V to 5V. Preset
timeout periods of 200ms (typ.) for PT7M6315USxxD3,
1570ms (typ.) for PT7M6315USxxD4, and 26ms for
PT7M6315USxxD2 are available.
Pin Configuration
PT7M6315USxxD3F/D4F
1
GND
VCC
4
2
RST
SOT143-4
MR
3
Pin Description
Name Type
RST
MR
I/O
I
P
P
Description
Reset Output:
RST is asserted when V
CC
drops below voltage threshold V
TH-
. Active low.
Manual Reset:
A logic low on MR asserts reset. Reset remains asserted as long as MR is low, and for the
reset timeout period (t
RS
) after the reset conditions are terminated. Connect to V
CC
if not used.
Ground
Supply Voltage.
GND
V
CC
2015-09-0002
1
PT0197-4
09/15/15
FPGA工程师全国薪资水平
大电子类工程师中FPGA工程师工资最高!! 41976...
chapman FPGA/CPLD
ARM指令TEXTAREA是什么意思?
TEXTAREA ;请问这句是什么意思 IMPORT main ...
alan_zhang ARM技术
你造嘛?电动汽车仅需一加仑汽油就可环游世界!
TI 公众号的文章,觉得这么多人一起做这么一个项目,很有意思,:pleased: 在吉尼斯记录挑战中,eLi14每100公里消耗81.16瓦时,相当于每10,956公里消耗1升高辛烷值汽油,换言之一加仑汽油便足 ......
john_wang 模拟与混合信号
求教:CAN总线通讯异常
大家好,请教个问题: 有一款CAN总线产品,在使用一段时间后,出现通讯异常。经客户排查,线束连接完好,客户初步进行如下测试: 1、上电测试CANH和CANL对GND的电压: ......
chenzhouyu 综合技术交流
Pads文件怎么转AD能打开的文件?
小白不明白, 老是有客户发Pads的文件给我, 但是我门这边又不支持Pads, 想知道怎么能打开Pads的文件, 或者要怎么转格式, 或者转为gerber格式? ...
捷配PCB打样 PCB设计
CE下如何实现画拖动的矩形?
这个拖动的矩形要在所有的窗口之上的,Windows 下我知道可以用获取桌面窗口后用DrawDragRect画,但是Windows CE下这样不行 但是Windows CE他自己带Title的窗口却是可以,不知道他们是如何实现的 ......
guochen82 嵌入式系统

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1837  2092  1265  2430  1210  37  43  26  49  25 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved