88W8688
Integrated MAC/Baseband/RF WLAN and Bluetooth SoC
Product Brief
PRODUCT OVERVIEW
The Marvell
®
88W8688 is a low-cost, low-power
highly-integrated IEEE 802.11a/g/b MAC/Baseband/RF
WLAN and Bluetooth Baseband/RF system-on-chip
(SoC). The device is designed to support IEEE 802.11a
or 802.11g payload data rates of 6, 9, 12, 18, 24, 36, 48,
and 54 Mbps, as well as 802.11b data rates of 1, 2, 5.5,
and 11 Mbps for WLAN operation. For Bluetooth
operation, the device supports Bluetooth 3.0 + High
Speed (HS) (also compliant with Bluetooth 2.1 + EDR).
The 88W8688 provides the combined functions of the
IEEE Standard 802.11/802.11b Direct Sequence Spread
Spectrum (DSSS), 802.11a/g Orthogonal Frequency
Division Multiplexing (OFDM) baseband modulation,
Medium Access Controller (MAC), CPU, memory, host
interfaces, direct-conversion WLAN RF radio, and
Bluetooth on a single integrated chip.
The core functional units of the 88W8688 are connected
with a high throughput interconnect system, as shown in
Figure 1.
The 88W8688 is equipped with a fully integrated RF to
baseband radio that operates in both the 2.4 GHz ISM
radio band for 802.11g/b WLAN applications and 5 GHz
UNII radio band for 802.11a WLAN applications. It also
contains all the circuitry to support both transmit and
receive for Bluetooth operation.
For optimum performance, the gain adjustment of the
integrated LNA and AGC on the receive path is
seamlessly controlled by baseband functions.
Integrated transmitters up-convert the quadrature
baseband signal, and then deliver the RF signals to
external power amplifiers for 2.4 GHz and 5 GHz radio
band transmission.
Local oscillator frequencies are generated by a fully
integrated programmable frequency synthesizer with no
external components. The loop bandwidth is optimized
for phase noise and dynamic performance and
quadrature signals are generated on-chip.
For security, the 88W8688 supports the IEEE 802.11i
security standard through implementation of the
Advanced Encryption Standard (AES)/Counter Mode
CBC-MAC Protocol (CCMP), and Wired Equivalent
Privacy (WEP) with Temporal Key Integrity Protocol
(TKIP) security mechanisms. The device also supports
Internet Protocol Security (IPsec) with DES/3DES/AES
encryption and MD5/SHA-1 authentication.
For video, voice, and multimedia applications, the
88W8688 supports 802.11e Quality of Service (QoS).
The device also supports 802.11h Dynamic Frequency
Selection (DFS) for detecting radar pulses when
operating in the 5 GHz range.
The 88W8688 supports a generic SPI (G-SPI) and SDIO
host interface for connecting the WLAN to the host
processor. High-speed UART, PCM/Inter-IC Sound (I
2
S),
and SDIO interfaces are available to connect the
Bluetooth core to the host processor. A Bluetooth
coexistence interface is also supported for external,
co-located Bluetooth devices.
Copyright © 2009 Marvell
November 30, 2009, 2.00
Doc. No. MV-S106650-00 Rev. F
Page 1
88W8688
Product Brief
Figure 1: Top Block Diagram
1
88W8688
I S, PCM, and
IEC 60958
Compatible Audio
CODEC Interface
2
Encryption
AES/CCMP
WEP/TKIP
IPsec
WLAN MAC/Baseband
802.11 MAC
Rx/Tx
Power
Management
802.11a/g/b
Baseband
(CCK/OFDM)
Demod
Modulator
ADC
DAC
Audio Interface
Audio Codec
Controller
Direct Conversion
Radio
802.11a
5 GHz Rx
802 .11g/b
2.4 GHz Rx
Rx
Rx
5 GHz
External PA
Tx
Tx
Osc
Processor
JTAG Interface
Feroceon
CPU
JTAG
C
P
U
B
U
S
CPU Interface
Interrupts
Timers
I
N
T
E
R
N
A
L
B
U
S
Bluetooth
Arbiter
BBU ADC
BBU DAC
802 .11a
5 GHz Tx
802.11g/b
2.4 GHz Tx
Antenna Select ,
T/R Switch
Power Enable Control
Serial IF
2.4 GHz
External PA
XTAL_IN/XO
XTAL_OUT
Bluetooth
Antenna
Bluetooth
Radio Unit
Bluetooth
Unit
SRAM
Bluetooth Coexistence Interface
Power Down
Sleep Clock
Host Interface
Host
Interface
Unit
G-SPI
G-SPI
Peripheral Bus
3-Wire, 4-Wire Serial Interface
2-Wire Serial Interface
1-Wire Serial Interface
SPI Serial EEPROM/PM
UART for Bluetooth Core
GPIO
Clocked
Serial Unit
UART
GPIO/LED
B
U
S
Peripheral
Bus Unit
DMA
SDIO
SDIO
1. Antenna can be used as an option to enhance performance.
Marvell reference designs are highly-integrated low cost, production quality designs that provide a quick
time-to-market solution for customers developing single chip IEEE 802.11a/g/b WLAN and Bluetooth solutions.
Doc. No. MV-S106650-00 Rev. F
Page 2
Copyright © 2009 Marvell
November 30, 2009, 2.00
Product Overview
Applications
Applications
WLAN/Bluetooth enabled cellular handsets
WLAN/Bluetooth headsets
Portable audio/video devices and accessories
Gaming platforms
WLAN/Bluetooth enabled digital still cameras and
printers
Packaging
6 x 10 mm 152-pin TFBGA
Flip chip package (400
μm)
Processor
CPU
Integrated Marvell Feroceon® CPU
(ARMv5TE-compliant)
Offloads wireless protocol stack processing from host
CPU
106 MHz operating frequency
General Features
Single-chip integration of 802.11a/g/b wireless direct
conversion radio, baseband, MAC, CPU, memory,
host interfaces, and Bluetooth
Integrates all 802.11a/g/b RF to baseband transmit
and receive operations, with support for external
power amplifiers
Fully integrated frequency synthesizers with
optimized phase noise performance for OFDM
applications
Ultra low-power dissipation
Supports 12, 13, 19.2, 20, 24, 26, 38.4, 40, or 52 MHz
oscillator clock source
Supports Marvell Bluetooth coexistence
DMA
Independent 2-channel Direct Memory Access (DMA)
Memory
Internal SRAM for Tx frame queues and Rx data
buffers
Boot ROM
Networking Functions
Standards
WLAN MAC
IEEE 802.11 WLAN
802.11 data rates of 1 and 2 Mbps
802.11b data rates of 5.5 and 11 Mbps
802.11a/g data rates of 6, 9, 12, 18, 24, 36, 48, and
54 Mbps for multimedia content transmission
802.11e Quality of Service (QoS)
802.11h DFS statistics processing
802.11h transmit power control
802.11j channels (Japan)
802.11s mesh networking
Ad-Hoc and Infrastructure modes
Request-to-Send (RTS)/Clear-to-Send (CTS) for
operation under Distributed Coordination Function
(DCF)
Hardware filtering of 64 multicast and 96 unicast
addresses and additional firmware options
On-chip Tx and Rx FIFOs for maximum throughput
Open System and Shared Key Authentication
services
Managed information base counters
Quality of Service (QoS)
DFS statistics processing
Mesh networking
Power management
External sleep clock control
Transmit rate adaptation
Transmit power control
Long and short preamble generation on a
frame-by-frame basis for 802.11b frames
Bluetooth
Bluetooth 3.0 + High Speed (HS) (also compliant
with Bluetooth 2.1 + EDR)
Bluetooth Class 1 (up to 10 dBm without external
PA) (Class 1.5)
Bluetooth Class 1 (greater than 10 dBm with
external PA)
Copyright © 2009 Marvell
November 30, 2009, 2.00
Doc. No. MV-S106650-00 Rev. F
Page 3
88W8688
Product Brief
WLAN Baseband
DSSS and OFDM modulation
Advanced Equalizer for Complementary Code Keying
(CCK) modes
Differential Binary Phase Shift Keying (DBPSK),
Differential Quadrature Phase Shift Keying (DQPSK),
and CCK modulation modes
16-QAM and 64-QAM modulation
On-chip A/D and D/A converters for
Inphase/Quadrature (I/Q) channels
Targeted for multi-path delay spreads up to 680 ns in
11 Mbps mode and 150 ns in 54 Mbps mode
DFS statistics gathering
802.11j channels (Japan)
WLAN Encryption
AES-CCMP hardware implementation as part of
802.11i security standard
WPA (Wi-Fi Protected Access) encryption
WEP 64- and 128-bit encryption with hardware TKIP
processing
IPsec security acceleration in hardware
Bluetooth
Digital Audio interfaces including PCM interface for
voice application and I
2
S for digital stereo
applications
Baseband and radio basic data rate and EDR
packet types—1 Mbps (GFSK), 2 Mbps
(p/4-DQPSK), and 3 Mbps (8DPSK)
Fully functional Bluetooth baseband—AFH, forward
error correction, header error control, access code
correlation, CRC, encryption bit stream generation,
and whitening
Adaptive Frequency Hopping (AFH), including
Packet Loss Rate (PLR)
Interlaced Scan for faster connection setup
Simultaneous active ACL connection support
Full master and slave piconet support
Scatternet support
Standard UART and SDIO Type-A HCI transport
layer
HCI layer verified to function with major profile stack
vendors
SCO/eSCO links with hardware accelerated audio
signal processing and hardware supported PPEC
algorithm for speech quality improvement
All standard SCO/eSCO voice coding
All standard pairing, authentication, link key, and
encryption operations
Standard Bluetooth power saving mechanisms (i.e.,
hold, sniff modes)
Dynamic Transmit Power Control (TPC)
Channel Quality Driven (CQD) data rate
WLAN RF
Rx Path
On-chip gain selectable LNA with optimized noise
figure and power consumption
Highly integrated architecture eliminates need for
external SAW filter
High dynamic range AGC function in receive mode
Immune to high power cellular phone transmission
signals
Supports antenna diversity
Tx Path
Supports external PA with power control for both
2.4 GHz and 5 GHz operation
Image-reject transmitter to reduce external RF filter
count for 2.4 GHz radio transmit
Supports closed and open loop power control in
increments of 0.5 dB
Very low spectral emissions in the cellular phone
receive band
Networking Coexistence
Supports Marvell 2-Wire Bluetooth Coexistence
Arbitration (2WBCA) scheme
Supports Marvell 3-Wire Bluetooth Coexistence
Arbitration (3WBCA) scheme
Supports Marvell 4-Wire Bluetooth Coexistence
Arbitration (4WBCA) scheme
Doc. No. MV-S106650-00 Rev. F
Page 4
Copyright © 2009 Marvell
November 30, 2009, 2.00
Product Overview
Host Interfaces
Host Interfaces
G-SPI device interface
SDIO device interface
•
Supports SPI, 1-bit SDIO, and 4-bit SDIO transfer
modes at the full clock range up to
50 MHz
Universal Asynchronous Receiver/Transmitter
(UART) interface
Audio Interfaces
Audio Codec Interface
Marvell Class D Audio Amplifier
TWSI interface for Audio Codec programming
IEC60958 compatible Audio Codec interface
I
2
S (Inter-IC Sound) interface for audio data
connection to Analog-to-Digital Converters (ADC) and
Digital-to-Analog Converters (DAC)
Master and slave mode for I
2
S, MSB, and LSB audio
interfaces
Tri-state output capability
Peripheral Bus Interfaces
Clocked serial unit
•
3-Wire, 4-Wire (3W4W) Serial Interface
•
2-Wire Serial Interface (TWSI)
•
1-Wire Serial Interface
•
SPI serial (EEPROM)
Universal Asynchronous Receiver/Transmitter
(UART)
General Purpose Input Output (GPIO)
Flexible GPIO interface with Light Emitting Diode
(LED) driver to indicate Tx/Rx activities
PCM Interface
Master or slave mode
PCM bit width size of 8 bits or 16 bits
Up to 4 slots with configurable bit width and start
positions
Short frame and long frame synchronization
Tri-state output capability
Copyright © 2009 Marvell
November 30, 2009, 2.00
Doc. No. MV-S106650-00 Rev. F
Page
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