PAS6329 Specification
PAS6329 CMOS VGA DIGITAL IMAGE SENSOR
General Description
The PAS6329 is a highly integrated CMOS active-pixel image sensor that has output of 640 x 480 pixels. It
embedded the new FinePixel™ sensor technology to perform the excellent image quality. PAS6329 outputs 8-bit
YUV/YCrCb 4:2:2 or RGB565/555/444 data through a parallel data bus. It is available in CSP-22L package.
The PAS6329 can be programmed to set the exposure time for different luminance condition via I2C
TM
serial
control bus. By programming the internal register set, it performs on-chip frame rate adjustment, offset correction
DAC and programmable gain control.
Features
Resolution: 640 x 480 pixels, 1/7” Lens
Bayer-RGB color filter array
Output format (parallel 8-bit):
YUV/YCrCb 4:2:2
RGB565/555/444
I2C
TM
Interface
Power dissipation: operating typical
25mA @ 2.8V (VGA YUV 30fps output,
without loading), power-down typical
10uA @ 2.8V
Automatic Background Compensation
DSP function:
AEC & AGC
AWB
Gamma
Color matrix
Sharpness
De-noise
Color saturation
Defect compensation
Lens shading compensation
Decimation
WOI & Sub-sampling
Dummy line & pixel timing
Output Hsync at Vsync
Module size : 6.0mm * 6.0mm
Key Specification
Resolution
Pixel Size
Array diagonal
Lens Chief Ray Angle
Color filter
Analog
Power
I/O
Core
Max. input clock
Max. output clock
Max. Frame rate
Scan Mode
Exposure Time
Sensitivity
S/N Ratio
Dynamic range
Package
640 (H) x 480 (V)
3.15um * 3.15um
1/7” Lens
25 degree
RGB Bayer Pattern
2.8V typical
2.8V typical
1.8V typical
52MHz
26MHz
30fps
Progressive
~ Frame time to Line time
1500mV/Lux-Sec
41dB
60dB
CSP-22L
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
1
PixArt Imaging Inc.
E-mail:
fae_service@pixart.com.tw
V1.0, 2011/03/03
PixArt Imaging Inc.
PAS6329
CMOS Image Sensor IC
1.
Pin Assignment
Pin No.
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C4
C5
D1
D3
D4
D5
E1
E2
E3
E4
E5
Name
SYSCLK
PXCLK
PXD1
PXD3
VSSD
VDDD
PXD0
PXD2
NC
PXD4
DVDD28
PXD6
PXD5
AVDD28
SCL
VSYNC
PXD7
VREF
VSSA
CSB
SDA
HSYNC
Type
IN
OUT
OUT
OUT
GND
PWR
OUT
OUT
--
OUT
PWR
OUT
OUT
PWR
IN
OUT
OUT
Ref
GND
IN
I/O
OUT
Description
External clock input
Pixel clock output
Digital pixel data [1]
Digital pixel data [3]
Digital ground
Digital core power, 1.8V
Digital pixel data [0], LSB
Digital pixel data [2]
--
Digital pixel data [4]
I/O power, 2.8V typical
Digital pixel data [6]
Digital pixel data [5]
Analog power, 2.8V typical
I2C clock input
Vertical synchronization signal output
Digital pixel data [7], MSB
Voltage reference
Analog ground
Power down mode enable, active high
I2C data
Horizontal synchronization signal output
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
2
PixArt Imaging Inc.
E-mail:
fae_service@pixart.com.tw
V1.0, 2011/03/03
PixArt Imaging Inc.
PAS6329
CMOS Image Sensor IC
2.
Specifications
Absolute Maximum Ratings
Operating Temperature
Stable Image Temperature
Ambient Storage Temperature
Supply Voltage ( with respect to ground )
All Input / Output Voltage ( with respect to ground )
Lead-free temperature, Surface-mount process
ESD rating, Human Body model
V
DDA
V
DDD
V
DDIO
-30℃ ~ 85℃
0℃ ~ 50℃
-40℃ ~ 125℃
4.5V
3.0V
4.5V
-0.3V to V
DDIO
+ 0.5V
245℃
2000V
DC Electrical Characteristics ( Ta = 0℃ ~ 70℃ )
Symbol
Parameter
Type : POWER
V
DDA
DC supply voltage – Analog
V
DDD
DC supply voltage – Digital core
V
DDIO
DC supply voltage – I/O
I
DD
Operating Current (VGA YUV 30fps / 2.8v)
I
PWDN
Power Down Current (VGA YUV 30fps / 2.8v)
Type : IN & I/O
V
IH
V
IL
Input Voltage HIGH
Input Voltage LOW
Type : OUT & I/O
V
OH
V
OL
Output Voltage HIGH
Output Voltage LOW
Min.
2.6
2.6
Typ.
2.8
1.8
2.8
25
10
Max.
3.0
3.0
Unit
V
V
V
mA
µA
V
V
DDIO
* 0.7
V
DDIO
* 0.3
V
DDIO
* 0.9
V
DDIO
* 0.1
V
V
V
AC Operating Condition
Symbol
f
sysclk
t
sysclk_dc
Sensor Characteristics
Parameter
System clock frequency
System clock duty cycle
Min.
45
Typ.
24
Max.
55
Unit
MHz
%
Parameter
Sensitivity
Signal to Noise Ratio
Dynamic Range
Typ.
1500
41
60
Unit
mV/Lux-Sec
dB
dB
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
3
PixArt Imaging Inc.
E-mail:
fae_service@pixart.com.tw
V1.0, 2011/03/03
PixArt Imaging Inc.
PAS6329
CMOS Image Sensor IC
3.
I2C
TM
Bus
PAS6329 supports I2C bus transfer protocol and acts as slave device. The 7-bits unique slave address is
“1000000” and supports receiving / transmitting speed as maximum 400KHz.
I2C Bus Overview
Only two wires SDA ( serial data ) and SCL ( serial clock ) carry information between the
devices connected to the I2C bus. Normally both SDA and SCL lines are open collector
structure and pulled high by external pull-up resistors.
Only the master can initiates a transfer ( start ), generates clock signals, and terminates a
transfer ( stop ).
Start and stop condition : A high to low transition of the SDA line while SCL is high defines a
start condition. A low to high transition of the SDA line while SCL is high defines a stop
condition. Please refer to Figure 2.1.
Valid data : The data on the SDA line must be stable during the high period of the SCL clock.
Within each byte, MSB is always transferred first. Read / Write control bit is the LSB of the
first byte. Please refer to Figure 2.2.
Both the master and slave can transmit and receive data from the bus.
Acknowledge : The receiving device should pull down the SDA line during high period of the
SCL clock line when a complete byte was transferred by transmitter. In the case of a master
received data from a slave, the master does not generate an acknowledgment on the last byte
to indicate the end of a master read cycle.
Figure 2.1 Start and Stop conditions
Figure 2.2 Valid Data
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
4
PixArt Imaging Inc.
E-mail:
fae_service@pixart.com.tw
V1.0, 2011/03/03
PixArt Imaging Inc.
PAS6329
CMOS Image Sensor IC
Data Transfer Format
Master transmits data to salve ( write cycle )
S : Start.
A : Acknowledge by salve.
P : Stop.
RW : The LSB of 1
ST
byte to decide whether current cycle is read or write cycle. RW = 1 –
Read cycle, RW = 0 – Write cycle.
SUBADDRESS : The address values of PAS6329 internal control registers. ( Please refer to
PAS6329 register description )
During write cycle, the master generates start condition and then places the 1
st
byte data that are
combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAS6329 )
issues acknowledgment, the master places 2
nd
byte ( Sub Address ) data on SDA line. Again follow the
PAS6329 acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS6329
control register ( address was assigned by 2
nd
byte ). After PAS6329 issues acknowledgment, the master
can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS6329
sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat
until last byte write. Every control registers value inside PAS6329 can be programming via this way.
Slave transmits data to master ( read cycle )
The sub-address was taken from previous write cycle.
The sub-address is automatically increment after each byte read.
Am : Acknowledge by master.
Note there is no acknowledgment from master after last byte read.
During read cycle, the master generates start condition and then place the 1
st
byte data that are combined
slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits
DATA was also placed on SDA line by PAS6329. The 8 bits data was read from PAS6329 internal control
register that address was assigned by previous write cycle. Follow the master acknowledgment, the
PAS6329 place the next 8 bits data ( address is increment automatically ) on SDA line and then transmit
to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is
no longer generated by master but instead by keep SDA line high. The slave ( PAS6329 ) must releases
SDA line to master to generate STOP condition.
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
5
PixArt Imaging Inc.
E-mail:
fae_service@pixart.com.tw
V1.0, 2011/03/03
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