2.5V, 3.3V Differential LVPECL Clock
Divider and Buffer
8T73S208A-01
DATA SHEET
General Description
The 8T73S208A-01 is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T73S208A-01 is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T73S208A-01 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I
2
C register. On
power-up, all outputs are disabled.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
One differential input reference clock
Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
Integrated input termination resistors
Eight LVPECL outputs
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum input clock frequency: 1GHz
LVCMOS interface levels for the control inputs
Individual output enable/disabled by I
2
C interface
Power-up state: all outputs disabled
Output skew: 60ps (maximum)
Output rise/fall times: 350ps (maximum)
Low additive phase jitter, RMS: 182fs (typical)
Full 2.5V and 3.3V supply voltages
Lead-free (RoHS 6) 32-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
Q0
nQ0
f
REF
Pin Assignment
ADR0
FSEL1
25
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
SDA
SCL
V
CC
nIN
V
T
27
IN
nIN
50
50
÷1, ÷2,
÷4, ÷8
Q1
nQ1
Q2
nQ2
Q3
nQ3
32
31
30
29
28
ADR1
V
EE
Q0
nQ0
Q1
1
2
3
4
5
6
7
8
IN
26
FSEL0
V
EE
nQ7
Q7
nQ6
Q6
V
EE
V
CCO
V
T
FSEL[1:0]
Pulldown (2)
2
Q4
nQ4
Q5
nQ5
I
2
C
2
8
nQ1
V
EE
V
CCO
SDA
SCL
ADR[1:0]
Pullup
Pullup
Pulldown (2)
nQ2
nQ3
nQ4
Q7
nQ7
32-pin, 5mm x 5mm VFQFN
8T73S208A-01 REVISION 1 06/15/15
1
©2015 Integrated Device Technology, Inc.
nQ5
Q3
Q4
Q5
Q2
Q6
nQ6
8T73S208A-01 DATA SHEET
Pin Descriptions and Pin Characteristics
Table 1. Pin Descriptions
Number
1,
32
2, 7, 18, 23
3, 4
5, 6
8, 17
9, 10
11, 12
13, 14
15, 16
19, 20
21, 22
24,
25
26
27
28
29
30
31
Name
ADR1, ADR0
V
EE
Q0, nQ0
Q1, nQ1
V
CCO
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
FSEL0,
FSEL1
IN
V
T
nIN
V
CC
SDA
SCL
Input
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Input
Input
Termination
Input
Input
Power
I/O
Input
Pullup
Pullup
Pulldown
Type
Pulldown
Description
I
2
C Address inputs. LVCMOS/LVTTL interface levels.
Negative supply pins.
Differential output pair 0. LVPECL interface levels.
Differential output pair 1. LVPECL interface levels.
Output supply pins.
Differential output pair 2. LVPECL interface levels.
Differential output pair 3. LVPECL interface levels.
Differential output pair 4. LVPECL interface levels.
Differential output pair 5. LVPECL interface levels.
Differential output pair 6. LVPECL interface levels.
Differential output pair 7. LVPECL interface levels.
Frequency divider select controls. See Table 3A for function.
LVCMOS/LVTTL interface levels.
Non-inverting differential clock input. RT = 50 termination to V
T.
Input for termination. Both IN and nIN inputs are internally terminated 50
to this pin. See input termination information in
Section, “Applications
Information”.
Inverting differential clock input. RT = 50 termination to V
T.
Power supply pin.
I
2
C Data Input/Output. Input: LVCMOS/LVTTL interface levels. Output:
open drain.
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
NOTE:
Pulldown
and
Pullup
refers to an internal input resistors. See
Section, “Table 2. Pin Characteristics”
values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND BUFFER
2
REVISION 1 06/15/15
8T73S208A-01 DATA SHEET
Function Tables
Input Frequency Divider Operation
The FSEL1 and FSEL0 control pins configure the input frequency
divider. In the default state (FSEL[1:0] are set to logic 0:0 or left open)
the output frequency is equal to the input frequency (divide-by-1).
The other FSEL[1:0] settings configure the input divider to
divide-by-2, 4 or 8, respectively.
variable bits which are set by the hardware pins ADR[1:0] (binary
11010, ADR1, ADR0). Bit 0 of slave address is used by the bus
controller to select either the read or write mode. The hardware pins
ADR1 and ADR0 and should be individually set by the user to avoid
address conflicts of multiple 8T73S208A-01 devices on the same
bus.
Table 3A. FSEL[1:0] Input Selection Function Table
Input
FSEL1
0 (default)
0
1
1
FSEL0
0 (default)
1
0
1
Operation
f
Q[7:0]
= f
REF
÷ 1
f
Q[7:0]
= f
REF
÷ 2
f
Q[7:0]
= f
REF
÷ 4
f
Q[7:0]
= f
REF
÷ 8
Table 3D. I
2
C Slave Address
7
1
6
1
5
0
4
1
3
0
2
ADR1
1
ADR0
0
R/W
SCL
NOTE: FSEL1, FSEL0 are asynchronous controls
SDA
Output Enable Operation
START
Valid Data
Acknowledge
STOP
The output enable/disable state of each individual differential output
Qx, nQx can be set by the content of the I
2
C register (see Table 3C).
A logic zero to an I
2
C bit in register 0 enables the corresponding
differential output, while a logic one disables the differential output
(see Table 3B). After each power cycle, the device resets all I
2
C bits
(Dn) to its default state (logic 1) and all Qx, nQx outputs are disabled.
After the first valid I
2
C write, the output enable state is controlled by
the I
2
C register. Setting and changing the output enable state through
the I
2
C interface is asynchronous to the input reference clock.
Figure 1: Standard I
2
C Transaction
START (S)
– defined as high-to-low transition on SDA while holding
SCL HIGH.
DATA
– between START and STOP cycles, SDA is synchronous with
SCL. Data may change only when SCL is LOW and must be stable
when SCL is HIGH.
ACKNOWLEDGE (A)
– SDA is driven LOW before the SCL rising
edge and held LOW until the SCL falling edge.
STOP (S)
– defined as low-to-high transition on SDA while holding
SCL HIGH
Table 3B. Individual Output Enable Control
Bit
Dn
0
1 (default)
Operation
Output Qx, nQx is enabled.
Output Qx, nQx is disabled in high-impedance
state.
S
DevAdd
W A
Data Byte
A P
Figure 2: Write Transaction
Table 3C. Individual output enable control
Bit
Output
Default
D7
Q7
1
D6
Q6
1
D5
Q5
1
D4
Q4
1
D3
Q3
1
D2
Q2
1
D1
Q1
1
D0
Q0
1
S
DevAdd
R A
Data Byte
A P
Figure 3: Read Transaction
S
–
W
–
R
–
A
–
DevAdd
–
P
–
Start or Repeated Start
R/W is set for Write
R/W is set for Read
Ack
7 bit Device Address
Stop
I
2
C Interface Protocol
The 8T73S208A-01 uses an I
2
C slave interface for writing and
reading the device configuration to and from the on-chip
configuration registers. This device uses the standard I
2
C write
format for a write transaction, and a standard I
2
C read format for a
read transaction. Figure 1 defines the I
2
C elements of the standard
I
2
C transaction. These elements consist of a start bit, data bytes, an
acknowledge or Not-Acknowledge bit and the stop bit. These
elements are arranged to make up the complete I
2
C transactions as
shown in Figure 2 and Figure 3. Figure 2 is a write transaction while
Figure 3 is read transaction. The 7-bit I
2
C slave address of the
8T73S208A-01 is a combination of a 5-bit fixed addresses and two
REVISION 1 06/15/15
3
2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND BUFFER
8T73S208A-01 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Input Termination Current, I
VT
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Storage Temperature, T
STG
Maximum Junction Temperature, T
JMAX
ESD - Human Body Model
1
ESD - Charged Device Model
NOTE 1:According to JEDEC/JS-001-2012/JESD22-C101E.
Rating
4.6V
-0.5V to V
CC
+ 0.5V
±35mA
50mA
100mA
-65C to 150C
125°C
2000V
500V
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCO
= 2.5V ± 5% or 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC
V
CCO
V
CCO
I
EE
Parameter
Power Supply Voltage
Power Supply Voltage
Output Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
3.135
2.375
3.135
Typical
2.5V
3.3V
2.5V
3.3V
88
Maximum
2.625
3.465
2.625
3.465
95
Units
V
V
V
V
mA
2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND BUFFER
4
REVISION 1 06/15/15
8T73S208A-01 DATA SHEET
Table 4B. LVCMOS/LVTTL Input DC Characteristics,
V
CC
= V
CCO
= 2.5V ± 5% or 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
Parameter
FSEL[1:0], ADR[1:0]
Input
High Voltage
1
SCL, SDA
FSEL[1:0], ADR[1:0]
SCL, SDA
FSEL[1:0], ADR[1:0]
V
IL
Input
Low Voltage
1
SCL, SDA
FSEL[1:0], ADR[1:0]
SCL, SDA
I
IH
Input
High Current
Input
Low Current
FSEL[1:0], ADR[1:0]
SCL, SDA
FSEL[1:0], ADR[1:0]
SCL, SDA
Test Conditions
V
CC
= 3.3V
± 5%
V
CC
= 3.3V
± 5%
V
CC
= 2.5V
± 5%
V
CC
= 2.5V
± 5%
V
CC
= 3.3V
± 5%
V
CC
= 3.3V
± 5%
V
CC
= 2.5V
± 5%
V
CC
= 2.5V
± 5%
V
CC
= V
IN
= 2.625 or 3.465V
V
CC
= V
IN
= 2.625 or 3.465V
V
CC
= 2.625 or 3.465V, V
IN
= 0V
V
CC
= 2.625 or 3.465V, V
IN
= 0V
-10
-150
Minimum
2.2
2.4
1.7
1.9
-0.3
-0.3
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3V
V
CC
+ 0.3V
V
CC
+ 0.3V
V
CC
+ 0.3V
0.8
0.8
0.7
0.5
150
10
Units
V
V
V
V
V
V
V
V
µA
µA
µA
µA
V
IH
I
IL
NOTE 1: V
IL
should not be lower than -0.3V and V
IH
should not be higher than V
CC
+ 0.3V.
Table 4C. Differential Input DC Characteristics,
V
CC
= V
CCO
= 2.5V ± 5% or 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IN
V
CMR
V
DIFF_IN
R
IN
R
IN_DIFF
Parameter
Input Voltage Swing
1
IN, nIN
Test Conditions
Minimum
0.15
1.2
0.3
IN, nIN to V
T
IN to nIN, V
T
= Open
40
80
50
100
Typical
Maximum
1.2
V
CC
– (V
PP
/2)
2.4
60
120
Units
V
V
V
Common Mode Input Voltage
1, 2
Differential Input Voltage Swing
Input Resistance
Differential
Input Resistance
IN, nIN
IN, nIN
NOTE 1: V
IL
should not be less than -0.3V and V
IH
should not be greater than V
CC
NOTE 2:
Common Mode Input Voltage
is defined as the cross point.
REVISION 1 06/15/15
5
2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND BUFFER
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