The 80C196KC 16-bit microcontroller is a high performance member of the MCS 96 microcontroller family
The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM 16 and 20 MHz operation and an
optional 16 Kbytes of ROM OTPROM Intel’s CHMOS III process provides a high performance processor
along with low power consumption
The 87C196KC is an 80C196KC with 16 Kbytes on-chip OTPROM The 83C196KC is an 80C196KC with 16
Kbytes factory programmed ROM In this document the 80C196KC will refer to all products unless otherwise
stated
Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are
available for pulse or waveform generation The high-speed output can also generate four software timers or
start an A D conversion Events can be based on the timer or up down counter
With the commercial (standard) temperature option operational characteristics are guaranteed over the tem-
perature range of 0 C to
a
70 C With the extended (Express) temperature range option operational charac-
teristics are guaranteed over the temperature range of
b
40 C to
a
85 C Unless otherwise noted the specifi-
cations are the same for both options
See the Packaging information for extended temperature designators
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1994
Order Number 270942-005
8XC196KC 8XC196KC20
270942 –1
Figure 1 8XC196KC Block Diagram
IOC3 (0CH HWIN1 READ WRITE)
270942 –45
NOTE
RSV Reserved bits must be
e
0
Figure 2 8XC196KC New SFR Bit (CLKOUT Disable)
2
8XC196KC 8XC196KC20
PROCESS INFORMATION
This device is manufactured on PX29 5 or PX29 9 a
CHMOS III process Additional process and reliabili-
ty information is available in Intel’s
Components
Quality and Reliability Handbook
Order Number
210997
Table 2 8XC196KC Memory Map
Description
External Memory or I O
Internal ROM OTPROM or External
Memory (Determined by EA)
Reserved Must contain FFH
(Note 5)
PTS Vectors
Upper Interrupt Vectors
ROM OTPROM Security Key
Reserved Must contain FFH
(Note 5)
270942 – 43
Address
0FFFFH
06000H
5FFFH
2080H
207FH
205EH
205DH
2040H
203FH
2030H
202FH
2020H
201FH
201AH
2019H
2018H
2017H
2014H
2013H
2000H
1FFFH
1FFEH
1FFDH
0200H
01FFH
0018H
0017H
0000H
Reserved Must Contain 20H
(Note 5)
CCB
Reserved Must contain FFH
(Note 5)
Lower Interrupt Vectors
EXAMPLE
N87C196KC is 68-Lead PLCC OTPROM
16 MHz
For complete package dimensional data refer to the
Intel Packaging Handbook (Order Number 240800)
NOTE
1 EPROMs are available as One Time Programmable
(OTPROM) only
Port 3 and Port 4
External Memory
488 Bytes Register RAM (Note 1)
Figure 3 The 8XC196KC Family Nomenclature
Table 1 Thermal Characteristics
Package
Type
PLCC
QFP
SQFP
i
ja
35 C W
55 C W
TBD
i
jc
13 C W
16 C W
TBD
CPU SFR’s (Notes 1 3 4)
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation Values will change
depending on operation conditions and application See
the Intel
Packaging Handbook
(order number 240800) for a
description of Intel’s thermal impedance test methodology
NOTES
1 Code executed in locations 0000H to 01FFH will be
forced external
2 Reserved memory locations must contain 0FFH unless
noted
3 Reserved SFR bit locations must contain 0
4 Refer to 8XC196KC User’s manual for SFR descriptions
5
WARNING
Reserved memory locations must not be
written or read The contents and or function of these lo-
cations may change with future revisions of the device
Therefore a program that relies on one or more of these
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